Lines Matching refs:ctrl
63 u32 ctrl;
65 ctrl = readl(rtcdev->base + CONTROL_REG);
66 ctrl &= ~CONTROL_STOP_BIT;
67 ctrl |= CONTROL_START_BIT;
68 writel(ctrl, rtcdev->base + CONTROL_REG);
101 u32 ctrl, prog;
110 ctrl = readl(rtcdev->base + CONTROL_REG);
111 ctrl &= ~CONTROL_STOP_BIT;
112 ctrl |= CONTROL_UPLOAD_BIT;
113 writel(ctrl, rtcdev->base + CONTROL_REG);
144 u32 mode, ctrl;
148 ctrl = readl(rtcdev->base + CONTROL_REG);
149 ctrl |= CONTROL_ALARM_OFF_BIT;
150 writel(ctrl, rtcdev->base + CONTROL_REG);
162 ctrl = readl(rtcdev->base + CONTROL_REG);
167 ctrl &= ~CONTROL_ALARM_OFF_BIT;
168 ctrl |= CONTROL_ALARM_ON_BIT;
170 ctrl &= ~CONTROL_STOP_BIT;
171 ctrl |= CONTROL_START_BIT;
172 writel(ctrl, rtcdev->base + CONTROL_REG);
181 u32 ctrl;
183 ctrl = readl(rtcdev->base + CONTROL_REG);
184 ctrl &= ~(CONTROL_ALARM_ON_BIT | CONTROL_ALARM_OFF_BIT | CONTROL_STOP_BIT);
187 ctrl |= CONTROL_ALARM_ON_BIT;
189 ctrl |= CONTROL_ALARM_OFF_BIT;
191 writel(ctrl, rtcdev->base + CONTROL_REG);