Lines Matching refs:val

157 	u32 val;
161 val = readl(wcss->reg_base + Q6SS_RESET_REG);
162 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
163 writel(val, wcss->reg_base + Q6SS_RESET_REG);
166 val = readl(wcss->reg_base + Q6SS_XO_CBCR);
167 val |= 0x1;
168 writel(val, wcss->reg_base + Q6SS_XO_CBCR);
172 val, !(val & BIT(31)), 1,
180 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
181 val |= Q6SS_BHS_ON;
182 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
186 val |= Q6SS_LDO_BYP;
187 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
190 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
191 val &= ~Q6SS_CLAMP_QMC_MEM;
192 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
195 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
196 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
199 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
201 val |= BIT(i);
202 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
208 val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
212 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
213 val &= ~Q6SS_CLAMP_WL;
214 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
217 val &= ~Q6SS_CLAMP_IO;
218 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
221 val = readl(wcss->reg_base + Q6SS_RESET_REG);
222 val &= ~Q6SS_CORE_ARES;
223 writel(val, wcss->reg_base + Q6SS_RESET_REG);
226 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
227 val |= Q6SS_CLK_ENABLE;
228 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
231 val = readl(wcss->reg_base + Q6SS_RESET_REG);
232 val &= ~Q6SS_STOP_CORE;
233 writel(val, wcss->reg_base + Q6SS_RESET_REG);
296 unsigned long val;
344 val = readl(wcss->reg_base + Q6SS_XO_CBCR);
345 val |= BIT(0);
346 writel(val, wcss->reg_base + Q6SS_XO_CBCR);
349 val, !(val & BIT(31)), 1,
360 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
361 val |= BIT(0);
362 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
370 val = readl(wcss->reg_base + Q6SS_RESET_REG);
371 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
372 writel(val, wcss->reg_base + Q6SS_RESET_REG);
395 val = readl(wcss->reg_base + Q6SS_RESET_REG);
396 val &= ~Q6SS_CORE_ARES;
397 writel(val, wcss->reg_base + Q6SS_RESET_REG);
400 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
401 val |= Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC;
402 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
412 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
413 val &= ~(Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC);
414 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
417 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
418 val &= ~Q6SS_CLK_ENABLE;
419 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
421 val = readl(wcss->reg_base + Q6SS_XO_CBCR);
422 val &= ~Q6SS_CLK_ENABLE;
423 writel(val, wcss->reg_base + Q6SS_XO_CBCR);
443 unsigned long val;
448 val = readl(wcss->reg_base + Q6SS_RESET_REG);
449 val &= ~Q6SS_STOP_CORE;
450 writel(val, wcss->reg_base + Q6SS_RESET_REG);
501 unsigned int val;
505 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
506 if (!ret && val)
515 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
516 if (ret || val || time_after(jiffies, timeout))
522 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
523 if (ret || !val)
532 unsigned long val;
538 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
539 val |= (Q6SS_CLAMP_IO | Q6SS_CLAMP_WL | Q6SS_CLAMP_QMC_MEM);
540 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
548 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
549 val &= ~Q6SS_BHS_ON;
550 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
558 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
559 val &= ~BIT(0);
560 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
562 val = readl(wcss->reg_base + Q6SS_XO_CBCR);
563 val &= ~BIT(0);
564 writel(val, wcss->reg_base + Q6SS_XO_CBCR);
569 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
570 val &= ~(Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC);
571 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
597 u32 val;
603 val = readl(wcss->rmb_base + SSCAON_CONFIG);
604 val |= SSCAON_ENABLE;
605 writel(val, wcss->rmb_base + SSCAON_CONFIG);
608 val |= SSCAON_BUS_EN;
609 val &= ~SSCAON_BUS_MUX_MASK;
610 writel(val, wcss->rmb_base + SSCAON_CONFIG);
613 val |= BIT(1);
614 writel(val, wcss->rmb_base + SSCAON_CONFIG);
618 val, (val & 0xffff) == 0x400, 1000,
630 val = readl(wcss->rmb_base + SSCAON_CONFIG);
631 val &= ~SSCAON_ENABLE;
632 writel(val, wcss->rmb_base + SSCAON_CONFIG);
643 u32 val;
650 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
651 val &= ~Q6SS_CLK_ENABLE;
652 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
655 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
656 val |= Q6SS_CLAMP_IO;
657 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
660 val |= QDSS_BHS_ON;
661 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
664 val &= ~Q6SS_L2DATA_STBY_N;
665 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
668 val &= ~Q6SS_SLP_RET_N;
669 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
673 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
674 val &= ~BIT(i);
675 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
680 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
681 val |= Q6SS_CLAMP_QMC_MEM;
682 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
685 val &= ~Q6SS_BHS_ON;
686 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
691 val, !(val & BHS_EN_REST_ACK), 1000,