Lines Matching defs:reg_base
172 void __iomem *reg_base;
627 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
629 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
631 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
640 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
642 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
655 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
657 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
659 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
668 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
670 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
672 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
681 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
683 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
686 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
692 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
714 qproc->reg_base + QDSP6SS_STRAP_ACC);
717 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
719 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
722 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
724 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
727 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
736 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
738 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
739 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
743 ret = readl_relaxed_poll_timeout(qproc->reg_base + QDSP6V62SS_BHS_STATUS,
754 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
760 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
762 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
766 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
778 val = readl(qproc->reg_base + mem_pwr_ctl);
781 writel(val, qproc->reg_base + mem_pwr_ctl);
787 val |= readl(qproc->reg_base + mem_pwr_ctl);
792 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
795 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
800 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
805 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
807 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
810 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
812 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
815 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
817 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
818 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
824 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
827 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
829 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
831 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
833 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
837 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
840 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
842 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
845 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
847 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
850 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
852 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
1257 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1260 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1712 qproc->reg_base = devm_platform_ioremap_resource_byname(pdev, "qdsp6");
1713 if (IS_ERR(qproc->reg_base))
1714 return PTR_ERR(qproc->reg_base);