Lines Matching refs:adsp
120 int (*shutdown)(struct qcom_adsp *adsp);
123 static int qcom_rproc_pds_attach(struct device *dev, struct qcom_adsp *adsp,
126 struct device **devs = adsp->proxy_pds;
144 if (num_pds > ARRAY_SIZE(adsp->proxy_pds))
164 static void qcom_rproc_pds_detach(struct qcom_adsp *adsp, struct device **pds,
167 struct device *dev = adsp->dev;
180 static int qcom_rproc_pds_enable(struct qcom_adsp *adsp, struct device **pds,
206 static void qcom_rproc_pds_disable(struct qcom_adsp *adsp, struct device **pds,
217 static int qcom_wpss_shutdown(struct qcom_adsp *adsp)
221 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
224 regmap_read_poll_timeout(adsp->halt_map,
225 adsp->halt_lpass + LPASS_HALTACK_REG, val,
229 reset_control_assert(adsp->pdc_sync_reset);
232 reset_control_assert(adsp->restart);
238 reset_control_deassert(adsp->restart);
241 reset_control_deassert(adsp->pdc_sync_reset);
245 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
247 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
250 regmap_read_poll_timeout(adsp->halt_map,
251 adsp->halt_lpass + LPASS_HALTACK_REG, val,
257 static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
264 val = readl(adsp->qdsp6ss_base + RET_CFG_REG);
266 writel(val, adsp->qdsp6ss_base + RET_CFG_REG);
268 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
271 ret = regmap_read(adsp->halt_map,
272 adsp->halt_lpass + LPASS_PWR_ON_REG, &val);
276 ret = regmap_read(adsp->halt_map,
277 adsp->halt_lpass + LPASS_MASTER_IDLE_REG,
282 regmap_write(adsp->halt_map,
283 adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
288 ret = regmap_read(adsp->halt_map,
289 adsp->halt_lpass + LPASS_HALTACK_REG, &val);
296 ret = regmap_read(adsp->halt_map,
297 adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
299 dev_err(adsp->dev, "port failed halt\n");
303 reset_control_assert(adsp->pdc_sync_reset);
305 reset_control_assert(adsp->restart);
310 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
313 reset_control_deassert(adsp->pdc_sync_reset);
315 reset_control_deassert(adsp->restart);
324 struct qcom_adsp *adsp = rproc->priv;
327 ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
328 adsp->mem_region, adsp->mem_phys,
329 adsp->mem_size, &adsp->mem_reloc);
333 qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
340 struct qcom_adsp *adsp = rproc->priv;
342 if (adsp->has_iommu)
343 iommu_unmap(rproc->domain, adsp->mem_phys, adsp->mem_size);
348 struct qcom_adsp *adsp = rproc->priv;
354 if (!adsp->has_iommu)
360 ret = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args);
367 iova = adsp->mem_phys | (sid << 32);
369 ret = iommu_map(rproc->domain, iova, adsp->mem_phys,
370 adsp->mem_size, IOMMU_READ | IOMMU_WRITE,
373 dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n");
382 struct qcom_adsp *adsp = rproc->priv;
386 ret = qcom_q6v5_prepare(&adsp->q6v5);
392 dev_err(adsp->dev, "ADSP smmu mapping failed\n");
396 ret = clk_prepare_enable(adsp->xo);
400 ret = qcom_rproc_pds_enable(adsp, adsp->proxy_pds,
401 adsp->proxy_pd_count);
405 ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks);
407 dev_err(adsp->dev, "adsp clk_enable failed\n");
412 writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);
415 writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);
418 writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);
421 writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
423 if (adsp->lpass_efuse)
424 writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse);
427 writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG);
430 writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG);
433 ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
436 dev_err(adsp->dev, "failed to bootup adsp\n");
440 ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ));
442 dev_err(adsp->dev, "start timed out\n");
449 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
451 qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
453 clk_disable_unprepare(adsp->xo);
457 qcom_q6v5_unprepare(&adsp->q6v5);
464 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
466 clk_disable_unprepare(adsp->xo);
467 qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
472 struct qcom_adsp *adsp = rproc->priv;
476 ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon);
478 dev_err(adsp->dev, "timed out on wait\n");
480 ret = adsp->shutdown(adsp);
482 dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
486 handover = qcom_q6v5_unprepare(&adsp->q6v5);
488 qcom_adsp_pil_handover(&adsp->q6v5);
495 struct qcom_adsp *adsp = rproc->priv;
498 offset = da - adsp->mem_reloc;
499 if (offset < 0 || offset + len > adsp->mem_size)
502 return adsp->mem_region + offset;
507 struct qcom_adsp *adsp = rproc->priv;
516 if (adsp->has_iommu) {
528 struct qcom_adsp *adsp = rproc->priv;
530 return qcom_q6v5_panic(&adsp->q6v5);
542 static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids)
547 adsp->xo = devm_clk_get(adsp->dev, "xo");
548 if (IS_ERR(adsp->xo)) {
549 ret = PTR_ERR(adsp->xo);
551 dev_err(adsp->dev, "failed to get xo clock");
558 adsp->num_clks = num_clks;
559 adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks,
560 sizeof(*adsp->clks), GFP_KERNEL);
561 if (!adsp->clks)
564 for (i = 0; i < adsp->num_clks; i++)
565 adsp->clks[i].id = clk_ids[i];
567 return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks);
570 static int adsp_init_reset(struct qcom_adsp *adsp)
572 adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev,
574 if (IS_ERR(adsp->pdc_sync_reset)) {
575 dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
576 return PTR_ERR(adsp->pdc_sync_reset);
579 adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart");
582 if (!adsp->restart)
583 adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass");
585 if (IS_ERR(adsp->restart)) {
586 dev_err(adsp->dev, "failed to acquire restart\n");
587 return PTR_ERR(adsp->restart);
593 static int adsp_init_mmio(struct qcom_adsp *adsp,
600 adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, 0);
601 if (IS_ERR(adsp->qdsp6ss_base)) {
602 dev_err(adsp->dev, "failed to map QDSP6SS registers\n");
603 return PTR_ERR(adsp->qdsp6ss_base);
608 adsp->lpass_efuse = NULL;
609 dev_dbg(adsp->dev, "failed to get efuse memory region\n");
611 adsp->lpass_efuse = devm_ioremap_resource(&pdev->dev, efuse_region);
612 if (IS_ERR(adsp->lpass_efuse)) {
613 dev_err(adsp->dev, "failed to map efuse registers\n");
614 return PTR_ERR(adsp->lpass_efuse);
623 adsp->halt_map = syscon_node_to_regmap(syscon);
625 if (IS_ERR(adsp->halt_map))
626 return PTR_ERR(adsp->halt_map);
629 1, &adsp->halt_lpass);
638 static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
643 node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
649 dev_err(adsp->dev, "unable to resolve memory-region\n");
653 adsp->mem_phys = adsp->mem_reloc = rmem->base;
654 adsp->mem_size = rmem->size;
655 adsp->mem_region = devm_ioremap_wc(adsp->dev,
656 adsp->mem_phys, adsp->mem_size);
657 if (!adsp->mem_region) {
658 dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
659 &rmem->base, adsp->mem_size);
670 struct qcom_adsp *adsp;
687 firmware_name, sizeof(*adsp));
697 adsp = rproc->priv;
698 adsp->dev = &pdev->dev;
699 adsp->rproc = rproc;
700 adsp->info_name = desc->sysmon_name;
701 adsp->has_iommu = desc->has_iommu;
703 platform_set_drvdata(pdev, adsp);
706 adsp->shutdown = qcom_wpss_shutdown;
708 adsp->shutdown = qcom_adsp_shutdown;
710 ret = adsp_alloc_memory_region(adsp);
714 ret = adsp_init_clock(adsp, desc->clk_ids);
718 ret = qcom_rproc_pds_attach(adsp->dev, adsp,
724 adsp->proxy_pd_count = ret;
726 ret = adsp_init_reset(adsp);
730 ret = adsp_init_mmio(adsp, pdev);
734 ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
739 qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);
740 qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
741 adsp->sysmon = qcom_add_sysmon_subdev(rproc,
744 if (IS_ERR(adsp->sysmon)) {
745 ret = PTR_ERR(adsp->sysmon);
756 qcom_rproc_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
766 struct qcom_adsp *adsp = platform_get_drvdata(pdev);
768 rproc_del(adsp->rproc);
770 qcom_q6v5_deinit(&adsp->q6v5);
771 qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
772 qcom_remove_sysmon_subdev(adsp->sysmon);
773 qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
774 qcom_rproc_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
775 rproc_free(adsp->rproc);
780 .firmware_name = "adsp.mdt",
782 .sysmon_name = "adsp",
798 .firmware_name = "adsp.pbn",
799 .load_state = "adsp",
801 .sysmon_name = "adsp",
849 { .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init },
851 { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },