Lines Matching refs:reg_base
155 val = readl(scp->reg_base + MT8183_SW_RSTN);
157 writel(val, scp->reg_base + MT8183_SW_RSTN);
164 val = readl(scp->reg_base + MT8183_SW_RSTN);
166 writel(val, scp->reg_base + MT8183_SW_RSTN);
171 writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
176 writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR);
183 scp_to_host = readl(scp->reg_base + MT8183_SCP_TO_HOST);
191 scp->reg_base + MT8183_SCP_TO_HOST);
198 scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET);
208 scp->reg_base + MT8192_SCP2APMCU_IPC_CLR);
211 writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ);
344 writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);
347 writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL);
348 writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL);
351 writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD);
352 writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
355 writel(0x0, scp->reg_base + MT8183_SCP_SRAM_PDN);
362 scp->reg_base + MT8183_SCP_CACHE_CON);
363 writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON);
389 writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);
392 writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL);
393 writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL);
396 scp_sram_power_on(scp->reg_base + MT8183_SCP_SRAM_PDN, 0);
399 writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD);
400 writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
401 writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1);
402 writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2);
409 scp->reg_base + MT8183_SCP_CACHE_CON);
410 writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON);
418 writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
420 writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
423 scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
424 scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
425 scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
426 scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
427 scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
430 writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
438 writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
440 writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
443 scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
444 scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
445 scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
446 scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
448 scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
451 writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
598 writel(0, scp->reg_base + MT8183_WDT_CFG);
604 scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
605 scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
606 scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
607 scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
608 scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
611 writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
617 scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
618 scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
619 scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
620 scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
622 scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
625 writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
860 scp->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
861 if (IS_ERR(scp->reg_base))
862 return dev_err_probe(dev, PTR_ERR(scp->reg_base),