Lines Matching refs:STM32_VREFBUF_CSR
20 #define STM32_VREFBUF_CSR 0x00
51 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
53 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
61 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val,
65 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
67 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
86 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
88 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
105 ret = readl_relaxed(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR;
124 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
126 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
144 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);