Lines Matching refs:size
98 * @sys_size: RapdiIO transport system size
857 u32 size, int *win_id)
869 bar_end = bar_base + pbar->size;
871 align = size/TSI721_PC2SR_ZONES;
890 if (win_base < (win->base + win->size) &&
891 (win_base + size) > win->base) {
893 win_base = win->base + win->size;
901 if (win_base + size > bar_end)
911 new_win->size = size;
914 pbar->free -= size;
920 u32 size, u32 flags, dma_addr_t *laddr)
933 "did=%d ra=0x%llx sz=0x%x", destid, rstart, size);
935 if (!is_power_of_2(size) || (size < 0x8000) || (rstart & (size - 1)))
942 if (priv->p2r_bar[i].free >= size) {
944 ret = tsi721_obw_alloc(priv, pbar, size, &obw);
964 zsize = size/TSI721_PC2SR_ZONES;
992 iowrite32(TSI721_OBWIN_SIZE(size) << 8,
1020 ob_win->pbar->free += ob_win->size;
1059 if (priv->p2r_bar[0].size == 0 && priv->p2r_bar[1].size == 0) {
1064 priv->p2r_bar[0].free = priv->p2r_bar[0].size;
1065 priv->p2r_bar[1].free = priv->p2r_bar[1].size;
1078 * @size: The mapping region size.
1087 u64 rstart, u64 size, u32 flags)
1100 /* Max IBW size supported by HW is 16GB */
1101 if (size > 0x400000000UL)
1105 /* Calculate minimal acceptable window size and base address */
1107 ibw_size = roundup_pow_of_two(size);
1111 "Direct (RIO_0x%llx -> PCIe_%pad), size=0x%llx, ibw_start = 0x%llx",
1112 rstart, &lstart, size, ibw_start);
1114 while ((lstart + size) > (ibw_start + ibw_size)) {
1117 /* Check for crossing IBW max size 16GB */
1130 "Translated (RIO_0x%llx -> PCIe_%pad), size=0x%llx",
1131 rstart, &lstart, size);
1133 if (!is_power_of_2(size) || size < 0x1000 ||
1134 ((u64)lstart & (size - 1)) || (rstart & (size - 1)))
1139 ibw_size = size;
1155 } else if (ibw_start < (ib_win->rstart + ib_win->size) &&
1169 (rstart + size) <= (ib_win->rstart +
1170 ib_win->size)) {
1197 ib_win->size = ibw_size;
1202 * When using direct IBW mapping and have larger than requested IBW size
1225 "Configured IBWIN%d (RIO_0x%llx -> PCIe_%pad), size=0x%llx",
1259 lstart < (ib_win->lstart + ib_win->size)) {
1471 "desc status FIFO @ %p (phys = %pad) size=0x%x",
1709 if (++priv->omsg_ring[mbox].tx_slot == priv->omsg_ring[mbox].size) {
1794 if (tx_slot == priv->omsg_ring[ch].size) {
1803 if (tx_slot >= priv->omsg_ring[ch].size)
1805 "OB_MSG tx_slot=%x > size=%x",
1806 tx_slot, priv->omsg_ring[ch].size);
1807 WARN_ON(tx_slot >= priv->omsg_ring[ch].size);
1811 if (tx_slot == priv->omsg_ring[ch].size)
1893 priv->omsg_ring[mbox].size = entries;
2034 for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
2086 (priv->omsg_ring[mbox].size + 1) *
2094 for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
2183 priv->imsg_ring[mbox].size = entries;
2187 for (i = 0; i < priv->imsg_ring[mbox].size; i++)
2322 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
2331 priv->imsg_ring[mbox].size * 8,
2339 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
2379 for (rx_slot = 0; rx_slot < priv->imsg_ring[mbox].size; rx_slot++)
2384 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
2392 priv->imsg_ring[mbox].size * 8,
2400 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
2430 if (++priv->imsg_ring[mbox].rx_slot == priv->imsg_ring[mbox].size)
2467 if (++rx_slot == priv->imsg_ring[mbox].size)
2486 if (++priv->imsg_ring[mbox].desc_rdptr == priv->imsg_ring[mbox].size)
2496 if (++priv->imsg_ring[mbox].fq_wrptr == priv->imsg_ring[mbox].size)
2794 priv->p2r_bar[0].size = priv->p2r_bar[1].size = 0;
2802 priv->p2r_bar[0].size = pci_resource_len(pdev, BAR_2);
2812 priv->p2r_bar[1].size = pci_resource_len(pdev, BAR_4);