Lines Matching defs:cycles
35 u64 cycles)
37 WARN_ON(cycles < 2 || cycles - 2 > priv->max);
40 return cycles - 2;
41 return priv->max - cycles + 2;
47 u64 cycles;
50 cycles = tlr + 2;
52 cycles = (u64)priv->max - tlr + 2;
54 /* cycles has a max of 2^32 + 2, so we can't overflow */
55 return DIV64_U64_ROUND_UP(cycles * NSEC_PER_SEC,
112 * To be representable by TLR, cycles must be between 2 and
113 * priv->max + 2. To enforce this we can reduce the cycles, but we may
126 /* Same thing for duty cycles */
138 /* Round down to 0% duty cycle for unrepresentable duty cycles */