Lines Matching refs:pc
181 static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan)
196 if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
204 if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
211 ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
221 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
230 c = pc->clk_rate;
239 c = pc->clk_rate;
250 if (pc->period_cycles[i] &&
251 (pc->period_cycles[i] != period_cycles)) {
266 pc->period_cycles[pwm->hwpwm] = period_cycles;
278 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);
285 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);
287 ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);
290 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
300 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
311 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
314 pc->polarity[pwm->hwpwm] = polarity;
321 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
338 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
341 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
344 configure_polarity(pc, pwm->hwpwm);
347 ret = clk_enable(pc->tbclk);
350 dev_name(pc->chip.dev), ret);
359 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
372 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
374 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
379 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
382 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
385 clk_disable(pc->tbclk);
393 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
401 pc->period_cycles[pwm->hwpwm] = 0;
453 struct ehrpwm_pwm_chip *pc;
457 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
458 if (!pc)
472 pc->clk_rate = clk_get_rate(clk);
473 if (!pc->clk_rate) {
478 pc->chip.dev = &pdev->dev;
479 pc->chip.ops = &ehrpwm_pwm_ops;
480 pc->chip.npwm = NUM_PWM_CHANNEL;
482 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);
483 if (IS_ERR(pc->mmio_base))
484 return PTR_ERR(pc->mmio_base);
487 pc->tbclk = devm_clk_get(&pdev->dev, "tbclk");
488 if (IS_ERR(pc->tbclk))
489 return dev_err_probe(&pdev->dev, PTR_ERR(pc->tbclk), "Failed to get tbclk\n");
491 ret = clk_prepare(pc->tbclk);
497 ret = pwmchip_add(&pc->chip);
503 platform_set_drvdata(pdev, pc);
509 clk_unprepare(pc->tbclk);
516 struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev);
518 pwmchip_remove(&pc->chip);
520 clk_unprepare(pc->tbclk);
526 static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc)
528 pm_runtime_get_sync(pc->chip.dev);
530 pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL);
531 pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD);
532 pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA);
533 pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB);
534 pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA);
535 pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB);
536 pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC);
537 pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC);
539 pm_runtime_put_sync(pc->chip.dev);
542 static void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc)
544 ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd);
545 ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa);
546 ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb);
547 ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla);
548 ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb);
549 ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc);
550 ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc);
551 ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl);
556 struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
559 ehrpwm_pwm_save_context(pc);
561 for (i = 0; i < pc->chip.npwm; i++) {
562 struct pwm_device *pwm = &pc->chip.pwms[i];
576 struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
579 for (i = 0; i < pc->chip.npwm; i++) {
580 struct pwm_device *pwm = &pc->chip.pwms[i];
589 ehrpwm_pwm_restore_context(pc);