Lines Matching defs:dd_freq
60 u32 dd_freq, duty, mode0, mode1;
89 * With clk_rate limited above we have dd_freq <= state->period,
92 dd_freq = mul_u64_u64_div_u64(clk_rate, state->period, (u64)SP7021_PWM_FREQ_SCALER
95 if (dd_freq == 0)
98 if (dd_freq > SP7021_PWM_FREQ_MAX)
99 dd_freq = SP7021_PWM_FREQ_MAX;
101 writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm));
118 (u64)dd_freq * NSEC_PER_SEC);
132 u32 mode0, dd_freq, duty;
139 dd_freq = readl(priv->base + SP7021_PWM_FREQ(pwm->hwpwm));
143 * dd_freq 16 bits, SP7021_PWM_FREQ_SCALER 8 bits
146 state->period = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)SP7021_PWM_FREQ_SCALER
149 * dd_freq 16 bits, duty 8 bits, NSEC_PER_SEC 30 bits, won't overflow.
151 state->duty_cycle = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)duty * NSEC_PER_SEC,