Lines Matching defs:sun4i_pwm
114 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
119 clk_rate = clk_get_rate(sun4i_pwm->clk);
123 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
131 sun4i_pwm->data->has_direct_mod_clk_output) {
140 sun4i_pwm->data->has_prescaler_bypass)
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
170 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
178 clk_rate = clk_get_rate(sun4i_pwm->clk);
180 *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
190 if (sun4i_pwm->data->has_prescaler_bypass) {
236 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
246 ret = clk_prepare_enable(sun4i_pwm->clk);
253 ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
258 clk_disable_unprepare(sun4i_pwm->clk);
262 spin_lock(&sun4i_pwm->ctrl_lock);
263 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
265 if (sun4i_pwm->data->has_direct_mod_clk_output) {
269 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
270 spin_unlock(&sun4i_pwm->ctrl_lock);
280 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
287 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
299 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
301 spin_unlock(&sun4i_pwm->ctrl_lock);
313 spin_lock(&sun4i_pwm->ctrl_lock);
314 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
317 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
318 spin_unlock(&sun4i_pwm->ctrl_lock);
320 clk_disable_unprepare(sun4i_pwm->clk);