Lines Matching defs:period
9 * and the currently running period is not guaranteed to be completed
132 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
133 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
165 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
182 (state->period * clk_rate >= NSEC_PER_SEC) &&
183 (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
194 * When not using any prescaler, the clock period in nanoseconds
198 div = clk_rate * state->period + NSEC_PER_SEC / 2;
214 div = div * state->period;
226 do_div(div, state->period);
238 u32 ctrl, duty = 0, period = 0, val;
253 ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
256 dev_err(chip->dev, "period exceeds the maximum value\n");
286 val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
306 /* We need a full period to elapse before disabling the channel. */
307 delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);