Lines Matching refs:spc
54 static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg)
58 return readl_relaxed(spc->base + offset);
61 static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid,
66 writel_relaxed(val, spc->base + offset);
72 struct sprd_pwm_chip *spc =
74 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
85 dev_err(spc->dev, "failed to enable pwm%u clocks\n",
90 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);
104 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE);
109 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY);
122 static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm,
125 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
155 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale);
156 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX);
157 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty);
165 struct sprd_pwm_chip *spc =
167 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
183 dev_err(spc->dev,
190 ret = sprd_pwm_config(spc, pwm, state->duty_cycle,
195 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1);
202 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0);
216 static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc)
222 struct sprd_pwm_chn *chn = &spc->chn[i];
229 ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM,
235 return dev_err_probe(spc->dev, ret,
244 dev_err(spc->dev, "no available PWM channels\n");
248 spc->num_pwms = i;
255 struct sprd_pwm_chip *spc;
258 spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL);
259 if (!spc)
262 spc->base = devm_platform_ioremap_resource(pdev, 0);
263 if (IS_ERR(spc->base))
264 return PTR_ERR(spc->base);
266 spc->dev = &pdev->dev;
267 platform_set_drvdata(pdev, spc);
269 ret = sprd_pwm_clk_init(spc);
273 spc->chip.dev = &pdev->dev;
274 spc->chip.ops = &sprd_pwm_ops;
275 spc->chip.npwm = spc->num_pwms;
277 ret = pwmchip_add(&spc->chip);
286 struct sprd_pwm_chip *spc = platform_get_drvdata(pdev);
288 pwmchip_remove(&spc->chip);