Lines Matching refs:rz_mtu3_pwm
134 rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm)
136 struct rz_mtu3_pwm_channel *priv = rz_mtu3_pwm->channel_data;
147 static bool rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
154 priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm);
169 struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
174 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
175 ch = priv - rz_mtu3_pwm->channel_data;
177 mutex_lock(&rz_mtu3_pwm->lock);
183 if (!rz_mtu3_pwm->user_count[ch]) {
186 mutex_unlock(&rz_mtu3_pwm->lock);
191 rz_mtu3_pwm->user_count[ch]++;
192 mutex_unlock(&rz_mtu3_pwm->lock);
199 struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
203 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
204 ch = priv - rz_mtu3_pwm->channel_data;
206 mutex_lock(&rz_mtu3_pwm->lock);
207 rz_mtu3_pwm->user_count[ch]--;
208 if (!rz_mtu3_pwm->user_count[ch])
211 mutex_unlock(&rz_mtu3_pwm->lock);
214 static int rz_mtu3_pwm_enable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
222 rc = pm_runtime_resume_and_get(rz_mtu3_pwm->chip.dev);
226 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
227 ch = priv - rz_mtu3_pwm->channel_data;
236 mutex_lock(&rz_mtu3_pwm->lock);
237 if (!rz_mtu3_pwm->enable_count[ch])
240 rz_mtu3_pwm->enable_count[ch]++;
241 mutex_unlock(&rz_mtu3_pwm->lock);
246 static void rz_mtu3_pwm_disable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
252 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
253 ch = priv - rz_mtu3_pwm->channel_data;
261 mutex_lock(&rz_mtu3_pwm->lock);
262 rz_mtu3_pwm->enable_count[ch]--;
263 if (!rz_mtu3_pwm->enable_count[ch])
266 mutex_unlock(&rz_mtu3_pwm->lock);
268 pm_runtime_put_sync(rz_mtu3_pwm->chip.dev);
274 struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
281 state->enabled = rz_mtu3_pwm_is_ch_enabled(rz_mtu3_pwm, pwm->hwpwm);
288 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
301 state->period = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
303 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
323 struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
332 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
333 ch = priv - rz_mtu3_pwm->channel_data;
335 period_cycles = mul_u64_u32_div(state->period, rz_mtu3_pwm->rate,
337 prescale = rz_mtu3_pwm_calculate_prescale(rz_mtu3_pwm, period_cycles);
345 if (rz_mtu3_pwm->enable_count[ch] > 1) {
346 if (rz_mtu3_pwm->prescale[ch] > prescale)
349 prescale = rz_mtu3_pwm->prescale[ch];
354 duty_cycles = mul_u64_u32_div(state->duty_cycle, rz_mtu3_pwm->rate,
373 if (rz_mtu3_pwm->prescale[ch] != prescale && rz_mtu3_pwm->enable_count[ch])
388 if (rz_mtu3_pwm->prescale[ch] != prescale) {
394 rz_mtu3_pwm->prescale[ch] = prescale;
396 if (rz_mtu3_pwm->enable_count[ch])
410 struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
419 rz_mtu3_pwm_disable(rz_mtu3_pwm, pwm);
424 mutex_lock(&rz_mtu3_pwm->lock);
426 mutex_unlock(&rz_mtu3_pwm->lock);
431 ret = rz_mtu3_pwm_enable(rz_mtu3_pwm, pwm);
446 struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev);
448 clk_disable_unprepare(rz_mtu3_pwm->clk);
455 struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev);
457 return clk_prepare_enable(rz_mtu3_pwm->clk);
466 struct rz_mtu3_pwm_chip *rz_mtu3_pwm = data;
468 clk_rate_exclusive_put(rz_mtu3_pwm->clk);
469 pm_runtime_disable(rz_mtu3_pwm->chip.dev);
470 pm_runtime_set_suspended(rz_mtu3_pwm->chip.dev);
476 struct rz_mtu3_pwm_chip *rz_mtu3_pwm;
481 rz_mtu3_pwm = devm_kzalloc(&pdev->dev, sizeof(*rz_mtu3_pwm), GFP_KERNEL);
482 if (!rz_mtu3_pwm)
485 rz_mtu3_pwm->clk = parent_ddata->clk;
491 rz_mtu3_pwm->channel_data[j].mtu = &parent_ddata->channels[i];
492 rz_mtu3_pwm->channel_data[j].mtu->dev = dev;
493 rz_mtu3_pwm->channel_data[j].map = &channel_map[j];
497 mutex_init(&rz_mtu3_pwm->lock);
498 platform_set_drvdata(pdev, rz_mtu3_pwm);
499 ret = clk_prepare_enable(rz_mtu3_pwm->clk);
503 clk_rate_exclusive_get(rz_mtu3_pwm->clk);
505 rz_mtu3_pwm->rate = clk_get_rate(rz_mtu3_pwm->clk);
510 if (rz_mtu3_pwm->rate > NSEC_PER_SEC) {
512 clk_rate_exclusive_put(rz_mtu3_pwm->clk);
518 rz_mtu3_pwm->chip.dev = &pdev->dev;
520 rz_mtu3_pwm);
524 rz_mtu3_pwm->chip.ops = &rz_mtu3_pwm_ops;
525 rz_mtu3_pwm->chip.npwm = RZ_MTU3_MAX_PWM_CHANNELS;
526 ret = devm_pwmchip_add(&pdev->dev, &rz_mtu3_pwm->chip);
535 clk_disable_unprepare(rz_mtu3_pwm->clk);