Lines Matching refs:mtu
53 * @mtu: MTU3 channel data
57 struct rz_mtu3_channel *mtu;
102 *pv_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_pv_offset);
103 *dc_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_dc_offset);
110 rz_mtu3_16bit_ch_write(priv->mtu, reg_pv_offset, pv_val);
111 rz_mtu3_16bit_ch_write(priv->mtu, reg_dc_offset, dc_val);
155 is_channel_en = rz_mtu3_is_enabled(priv->mtu);
160 val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORH);
162 val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORL);
184 is_mtu3_channel_available = rz_mtu3_request_channel(priv->mtu);
209 rz_mtu3_release_channel(priv->mtu);
230 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_MD_PWMMODE1);
232 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, val);
234 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, val);
238 rz_mtu3_enable(priv->mtu);
257 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, RZ_MTU3_TIOR_OC_RETAIN);
259 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, RZ_MTU3_TIOR_OC_RETAIN);
264 rz_mtu3_disable(priv->mtu);
296 val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TCR);
374 rz_mtu3_disable(priv->mtu);
377 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR,
382 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR,
397 rz_mtu3_enable(priv->mtu);
491 rz_mtu3_pwm->channel_data[j].mtu = &parent_ddata->channels[i];
492 rz_mtu3_pwm->channel_data[j].mtu->dev = dev;