Lines Matching defs:period
42 unsigned long period;
81 tmp = readl_relaxed(pc->base + pc->data->regs.period);
83 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
107 unsigned long period, duty;
114 * Since period and duty cycle registers have a width of 32
115 * bits, every possible input period can be obtained using the
118 div = clk_rate * state->period;
119 period = DIV_ROUND_CLOSEST_ULL(div,
126 * Lock the period and duty of previous configuration, then
127 * change the duty and period, that would not be effective.
135 writel(period, pc->base + pc->data->regs.period);
148 * the configuration of duty, period and polarity
149 * would be effective together at next period.
237 .period = 0x08,
250 .period = 0x04,
264 .period = 0x04,
278 .period = 0x04,