Lines Matching defs:tpu
72 struct tpu_device *tpu;
94 void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET
105 dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",
132 spin_lock_irqsave(&tpd->tpu->lock, flags);
133 value = ioread16(tpd->tpu->base + TPU_TSTR);
140 iowrite16(value, tpd->tpu->base + TPU_TSTR);
141 spin_unlock_irqrestore(&tpd->tpu->lock, flags);
150 pm_runtime_get_sync(&tpd->tpu->pdev->dev);
151 ret = clk_prepare_enable(tpd->tpu->clk);
153 dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");
182 dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
200 clk_disable_unprepare(tpd->tpu->clk);
201 pm_runtime_put(&tpd->tpu->pdev->dev);
212 struct tpu_device *tpu = to_tpu_device(chip);
222 tpd->tpu = tpu;
248 struct tpu_device *tpu = to_tpu_device(chip);
256 clk_rate = clk_get_rate(tpu->clk);
310 dev_dbg(&tpu->pdev->dev,
332 dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,
443 struct tpu_device *tpu;
446 tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
447 if (tpu == NULL)
450 spin_lock_init(&tpu->lock);
451 tpu->pdev = pdev;
454 tpu->base = devm_platform_ioremap_resource(pdev, 0);
455 if (IS_ERR(tpu->base))
456 return PTR_ERR(tpu->base);
458 tpu->clk = devm_clk_get(&pdev->dev, NULL);
459 if (IS_ERR(tpu->clk))
460 return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n");
463 platform_set_drvdata(pdev, tpu);
465 tpu->chip.dev = &pdev->dev;
466 tpu->chip.ops = &tpu_pwm_ops;
467 tpu->chip.npwm = TPU_CHANNEL_MAX;
473 ret = devm_pwmchip_add(&pdev->dev, &tpu->chip);
482 { .compatible = "renesas,tpu-r8a73a4", },
483 { .compatible = "renesas,tpu-r8a7740", },
484 { .compatible = "renesas,tpu-r8a7790", },
485 { .compatible = "renesas,tpu", },
495 .name = "renesas-tpu-pwm",
505 MODULE_ALIAS("platform:renesas-tpu-pwm");