Lines Matching defs:tpd
92 static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value)
94 void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET
95 + tpd->channel * TPU_CHANNEL_SIZE;
100 static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd,
105 dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",
106 tpd->channel, states[state]);
110 tpu_pwm_write(tpd, TPU_TIORn,
111 tpd->polarity == PWM_POLARITY_INVERSED ?
115 tpu_pwm_write(tpd, TPU_TIORn,
116 tpd->polarity == PWM_POLARITY_INVERSED ?
120 tpu_pwm_write(tpd, TPU_TIORn,
121 tpd->polarity == PWM_POLARITY_INVERSED ?
127 static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start)
132 spin_lock_irqsave(&tpd->tpu->lock, flags);
133 value = ioread16(tpd->tpu->base + TPU_TSTR);
136 value |= 1 << tpd->channel;
138 value &= ~(1 << tpd->channel);
140 iowrite16(value, tpd->tpu->base + TPU_TSTR);
141 spin_unlock_irqrestore(&tpd->tpu->lock, flags);
144 static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd)
148 if (!tpd->timer_on) {
150 pm_runtime_get_sync(&tpd->tpu->pdev->dev);
151 ret = clk_prepare_enable(tpd->tpu->clk);
153 dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");
156 tpd->timer_on = true;
164 tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
165 tpu_pwm_start_stop(tpd, false);
175 tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
176 tpd->prescaler);
177 tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM);
178 tpu_pwm_set_pin(tpd, TPU_PIN_PWM);
179 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
180 tpu_pwm_write(tpd, TPU_TGRBn, tpd->period);
182 dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
183 tpd->channel, tpd->duty, tpd->period);
186 tpu_pwm_start_stop(tpd, true);
191 static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd)
193 if (!tpd->timer_on)
197 tpu_pwm_start_stop(tpd, false);
200 clk_disable_unprepare(tpd->tpu->clk);
201 pm_runtime_put(&tpd->tpu->pdev->dev);
203 tpd->timer_on = false;
213 struct tpu_pwm_device *tpd;
218 tpd = kzalloc(sizeof(*tpd), GFP_KERNEL);
219 if (tpd == NULL)
222 tpd->tpu = tpu;
223 tpd->channel = pwm->hwpwm;
224 tpd->polarity = PWM_POLARITY_NORMAL;
225 tpd->prescaler = 0;
226 tpd->period = 0;
227 tpd->duty = 0;
229 tpd->timer_on = false;
231 pwm_set_chip_data(pwm, tpd);
238 struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
240 tpu_pwm_timer_stop(tpd);
241 kfree(tpd);
247 struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
314 if (tpd->prescaler == prescaler && tpd->period == period)
317 tpd->prescaler = prescaler;
318 tpd->period = period;
319 tpd->duty = duty;
325 if (duty_only && tpd->timer_on) {
331 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
332 dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,
333 tpd->duty);
336 ret = tpu_pwm_timer_start(tpd);
346 tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
347 tpu_pwm_timer_stop(tpd);
356 struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
358 tpd->polarity = polarity;
365 struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
368 ret = tpu_pwm_timer_start(tpd);
376 if (tpd->duty == 0 || tpd->duty == tpd->period) {
377 tpu_pwm_set_pin(tpd, tpd->duty ?
379 tpu_pwm_timer_stop(tpd);
387 struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
390 tpu_pwm_timer_start(tpd);
391 tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
392 tpu_pwm_timer_stop(tpd);