Lines Matching refs:mdp
58 static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
61 void __iomem *address = mdp->base + offset;
73 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
81 if (!state->enabled && mdp->enabled) {
82 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN,
83 mdp->data->enable_mask, 0x0);
84 clk_disable_unprepare(mdp->clk_mm);
85 clk_disable_unprepare(mdp->clk_main);
87 mdp->enabled = false;
91 if (!mdp->enabled) {
92 err = clk_prepare_enable(mdp->clk_main);
94 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n",
99 err = clk_prepare_enable(mdp->clk_mm);
101 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n",
103 clk_disable_unprepare(mdp->clk_main);
118 rate = clk_get_rate(mdp->clk_main);
122 if (!mdp->enabled) {
123 clk_disable_unprepare(mdp->clk_mm);
124 clk_disable_unprepare(mdp->clk_main);
137 if (mdp->data->bls_debug && !mdp->data->has_commit) {
142 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
143 mdp->data->bls_debug_mask,
144 mdp->data->bls_debug_mask);
145 mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
146 mdp->data->con0_sel,
147 mdp->data->con0_sel);
150 mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
153 mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
157 if (mdp->data->has_commit) {
158 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
159 mdp->data->commit_mask,
160 mdp->data->commit_mask);
161 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
162 mdp->data->commit_mask,
166 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
167 mdp->data->enable_mask);
168 mdp->enabled = true;
177 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
182 err = clk_prepare_enable(mdp->clk_main);
184 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
188 err = clk_prepare_enable(mdp->clk_mm);
190 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
191 clk_disable_unprepare(mdp->clk_main);
200 if (mdp->data->bls_debug)
201 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
202 mdp->data->bls_debug_mask,
203 mdp->data->bls_debug_mask);
205 rate = clk_get_rate(mdp->clk_main);
206 con0 = readl(mdp->base + mdp->data->con0);
207 con1 = readl(mdp->base + mdp->data->con1);
208 pwm_en = readl(mdp->base + DISP_PWM_EN);
209 state->enabled = !!(pwm_en & mdp->data->enable_mask);
221 clk_disable_unprepare(mdp->clk_mm);
222 clk_disable_unprepare(mdp->clk_main);
235 struct mtk_disp_pwm *mdp;
238 mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
239 if (!mdp)
242 mdp->data = of_device_get_match_data(&pdev->dev);
244 mdp->base = devm_platform_ioremap_resource(pdev, 0);
245 if (IS_ERR(mdp->base))
246 return PTR_ERR(mdp->base);
248 mdp->clk_main = devm_clk_get(&pdev->dev, "main");
249 if (IS_ERR(mdp->clk_main))
250 return PTR_ERR(mdp->clk_main);
252 mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
253 if (IS_ERR(mdp->clk_mm))
254 return PTR_ERR(mdp->clk_mm);
256 mdp->chip.dev = &pdev->dev;
257 mdp->chip.ops = &mtk_disp_pwm_ops;
258 mdp->chip.npwm = 1;
260 ret = pwmchip_add(&mdp->chip);
266 platform_set_drvdata(pdev, mdp);
273 struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
275 pwmchip_remove(&mdp->chip);