Lines Matching defs:value
211 u32 value;
222 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
224 writel(value, meson->base + channel_data->reg_offset);
226 value = readl(meson->base + REG_MISC_AB);
227 value |= channel_data->pwm_en_mask;
228 writel(value, meson->base + REG_MISC_AB);
236 u32 value;
240 value = readl(meson->base + REG_MISC_AB);
241 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
242 writel(value, meson->base + REG_MISC_AB);
260 * highest rate and minimum divider value, resulting
310 u32 value;
318 value = readl(meson->base + REG_MISC_AB);
319 state->enabled = value & channel_data->pwm_en_mask;
321 value = readl(meson->base + channel_data->reg_offset);
322 channel->lo = FIELD_GET(PWM_LOW_MASK, value);
323 channel->hi = FIELD_GET(PWM_HIGH_MASK, value);