Lines Matching defs:lpc18xx_pwm
116 static inline void lpc18xx_pwm_writel(struct lpc18xx_pwm_chip *lpc18xx_pwm,
119 writel(val, lpc18xx_pwm->base + reg);
122 static inline u32 lpc18xx_pwm_readl(struct lpc18xx_pwm_chip *lpc18xx_pwm,
125 return readl(lpc18xx_pwm->base + reg);
128 static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm,
134 mutex_lock(&lpc18xx_pwm->res_lock);
141 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE);
144 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val);
146 mutex_unlock(&lpc18xx_pwm->res_lock);
151 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
157 * As period_ns >= min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, lpc18xx_pwm->clk_rate);
160 val = mul_u64_u64_div_u64(period_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
162 lpc18xx_pwm_writel(lpc18xx_pwm,
163 LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event),
166 lpc18xx_pwm_writel(lpc18xx_pwm,
167 LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event),
174 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
175 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
182 val = mul_u64_u64_div_u64(duty_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
184 lpc18xx_pwm_writel(lpc18xx_pwm,
188 lpc18xx_pwm_writel(lpc18xx_pwm,
196 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
199 if (period_ns < lpc18xx_pwm->min_period_ns ||
200 period_ns > lpc18xx_pwm->max_period_ns) {
205 mutex_lock(&lpc18xx_pwm->period_lock);
207 requested_events = bitmap_weight(&lpc18xx_pwm->event_map,
215 if (requested_events > 2 && lpc18xx_pwm->period_ns != period_ns &&
216 lpc18xx_pwm->period_ns) {
219 mutex_unlock(&lpc18xx_pwm->period_lock);
223 if ((requested_events <= 2 && lpc18xx_pwm->period_ns != period_ns) ||
224 !lpc18xx_pwm->period_ns) {
225 lpc18xx_pwm->period_ns = period_ns;
231 mutex_unlock(&lpc18xx_pwm->period_lock);
240 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
241 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
245 lpc18xx_pwm_writel(lpc18xx_pwm,
250 lpc18xx_pwm_writel(lpc18xx_pwm,
255 set_event = lpc18xx_pwm->period_event;
260 clear_event = lpc18xx_pwm->period_event;
264 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm),
266 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm),
268 lpc18xx_pwm_set_conflict_res(lpc18xx_pwm, pwm, res_action);
275 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
276 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
278 lpc18xx_pwm_writel(lpc18xx_pwm,
280 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0);
281 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0);
286 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
287 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
290 event = find_first_zero_bit(&lpc18xx_pwm->event_map,
294 dev_err(lpc18xx_pwm->dev,
299 set_bit(event, &lpc18xx_pwm->event_map);
307 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
308 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
310 clear_bit(lpc18xx_data->duty_event, &lpc18xx_pwm->event_map);
355 struct lpc18xx_pwm_chip *lpc18xx_pwm;
359 lpc18xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*lpc18xx_pwm),
361 if (!lpc18xx_pwm)
364 lpc18xx_pwm->dev = &pdev->dev;
366 lpc18xx_pwm->base = devm_platform_ioremap_resource(pdev, 0);
367 if (IS_ERR(lpc18xx_pwm->base))
368 return PTR_ERR(lpc18xx_pwm->base);
370 lpc18xx_pwm->pwm_clk = devm_clk_get_enabled(&pdev->dev, "pwm");
371 if (IS_ERR(lpc18xx_pwm->pwm_clk))
372 return dev_err_probe(&pdev->dev, PTR_ERR(lpc18xx_pwm->pwm_clk),
375 lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk);
376 if (!lpc18xx_pwm->clk_rate)
383 if (lpc18xx_pwm->clk_rate > NSEC_PER_SEC)
386 mutex_init(&lpc18xx_pwm->res_lock);
387 mutex_init(&lpc18xx_pwm->period_lock);
389 lpc18xx_pwm->max_period_ns =
390 mul_u64_u64_div_u64(NSEC_PER_SEC, LPC18XX_PWM_TIMER_MAX, lpc18xx_pwm->clk_rate);
392 lpc18xx_pwm->min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC,
393 lpc18xx_pwm->clk_rate);
395 lpc18xx_pwm->chip.dev = &pdev->dev;
396 lpc18xx_pwm->chip.ops = &lpc18xx_pwm_ops;
397 lpc18xx_pwm->chip.npwm = LPC18XX_NUM_PWMS;
400 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CONFIG,
407 set_bit(LPC18XX_PWM_EVENT_PERIOD, &lpc18xx_pwm->event_map);
408 lpc18xx_pwm->period_event = LPC18XX_PWM_EVENT_PERIOD;
410 lpc18xx_pwm_writel(lpc18xx_pwm,
411 LPC18XX_PWM_EVSTATEMSK(lpc18xx_pwm->period_event),
414 val = LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_pwm->period_event) |
416 lpc18xx_pwm_writel(lpc18xx_pwm,
417 LPC18XX_PWM_EVCTRL(lpc18xx_pwm->period_event), val);
419 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_LIMIT,
420 BIT(lpc18xx_pwm->period_event));
422 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
427 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, val);
429 ret = pwmchip_add(&lpc18xx_pwm->chip);
433 platform_set_drvdata(pdev, lpc18xx_pwm);
440 struct lpc18xx_pwm_chip *lpc18xx_pwm = platform_get_drvdata(pdev);
443 pwmchip_remove(&lpc18xx_pwm->chip);
445 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
446 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL,