Lines Matching refs:val
72 u32 val;
127 p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period);
140 u32 rate, val, prescale;
148 val = readl(tpm->base + PWM_IMX_TPM_SC);
149 prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
155 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
156 if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED)
166 state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
180 u32 val, cmod, cur_prescale;
194 val = readl(tpm->base + PWM_IMX_TPM_SC);
195 cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val);
196 cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
201 val &= ~PWM_IMX_TPM_SC_PS;
202 val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale);
203 writel(val, tpm->base + PWM_IMX_TPM_SC);
233 writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
243 != p->val) {
256 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
257 val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA |
267 val |= PWM_IMX_TPM_CnSC_MSB;
268 val |= (state->polarity == PWM_POLARITY_NORMAL) ?
272 writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
276 val = readl(tpm->base + PWM_IMX_TPM_SC);
279 val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK;
282 val &= ~PWM_IMX_TPM_SC_CMOD;
284 writel(val, tpm->base + PWM_IMX_TPM_SC);
342 u32 val;
370 val = readl(tpm->base + PWM_IMX_TPM_PARAM);
371 tpm->chip.npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val);