Lines Matching refs:imgchip
80 static inline void img_pwm_writel(struct img_pwm_chip *imgchip,
83 writel(val, imgchip->base + reg);
86 static inline u32 img_pwm_readl(struct img_pwm_chip *imgchip, u32 reg)
88 return readl(imgchip->base + reg);
96 struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
97 unsigned int max_timebase = imgchip->data->max_timebase;
100 if (period_ns < imgchip->min_period_ns ||
101 period_ns > imgchip->max_period_ns) {
106 input_clk_hz = clk_get_rate(imgchip->pwm_clk);
134 val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
138 img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
142 img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);
153 struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
160 val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
162 img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
164 regmap_clear_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,
174 struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
176 val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
178 img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
229 struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
231 clk_disable_unprepare(imgchip->pwm_clk);
232 clk_disable_unprepare(imgchip->sys_clk);
239 struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
242 ret = clk_prepare_enable(imgchip->sys_clk);
248 ret = clk_prepare_enable(imgchip->pwm_clk);
251 clk_disable_unprepare(imgchip->sys_clk);
263 struct img_pwm_chip *imgchip;
266 imgchip = devm_kzalloc(&pdev->dev, sizeof(*imgchip), GFP_KERNEL);
267 if (!imgchip)
270 imgchip->dev = &pdev->dev;
272 imgchip->base = devm_platform_ioremap_resource(pdev, 0);
273 if (IS_ERR(imgchip->base))
274 return PTR_ERR(imgchip->base);
279 imgchip->data = of_dev_id->data;
281 imgchip->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
283 if (IS_ERR(imgchip->periph_regs))
284 return PTR_ERR(imgchip->periph_regs);
286 imgchip->sys_clk = devm_clk_get(&pdev->dev, "sys");
287 if (IS_ERR(imgchip->sys_clk)) {
289 return PTR_ERR(imgchip->sys_clk);
292 imgchip->pwm_clk = devm_clk_get(&pdev->dev, "imgchip");
293 if (IS_ERR(imgchip->pwm_clk)) {
294 dev_err(&pdev->dev, "failed to get imgchip clock\n");
295 return PTR_ERR(imgchip->pwm_clk);
298 platform_set_drvdata(pdev, imgchip);
309 clk_rate = clk_get_rate(imgchip->pwm_clk);
311 dev_err(&pdev->dev, "imgchip clock has no frequency\n");
317 val = (u64)NSEC_PER_SEC * 512 * imgchip->data->max_timebase;
319 imgchip->max_period_ns = val;
323 imgchip->min_period_ns = val;
325 imgchip->chip.dev = &pdev->dev;
326 imgchip->chip.ops = &img_pwm_ops;
327 imgchip->chip.npwm = IMG_PWM_NPWM;
329 ret = pwmchip_add(&imgchip->chip);
348 struct img_pwm_chip *imgchip = platform_get_drvdata(pdev);
354 pwmchip_remove(&imgchip->chip);
360 struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
369 for (i = 0; i < imgchip->chip.npwm; i++)
370 imgchip->suspend_ch_cfg[i] = img_pwm_readl(imgchip,
373 imgchip->suspend_ctrl_cfg = img_pwm_readl(imgchip, PWM_CTRL_CFG);
382 struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
390 for (i = 0; i < imgchip->chip.npwm; i++)
391 img_pwm_writel(imgchip, PWM_CH_CFG(i),
392 imgchip->suspend_ch_cfg[i]);
394 img_pwm_writel(imgchip, PWM_CTRL_CFG, imgchip->suspend_ctrl_cfg);
396 for (i = 0; i < imgchip->chip.npwm; i++)
397 if (imgchip->suspend_ctrl_cfg & BIT(i))
398 regmap_clear_bits(imgchip->periph_regs,