Lines Matching defs:fpc
61 static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
65 regmap_read(fpc->regmap, FTM_FMS, &val);
67 regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
70 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
72 regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
90 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
92 ret = clk_prepare_enable(fpc->ipg_clk);
93 if (!ret && fpc->soc->has_enable_bits) {
94 mutex_lock(&fpc->lock);
95 regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
96 mutex_unlock(&fpc->lock);
104 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
106 if (fpc->soc->has_enable_bits) {
107 mutex_lock(&fpc->lock);
108 regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
109 mutex_unlock(&fpc->lock);
112 clk_disable_unprepare(fpc->ipg_clk);
115 static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
121 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
124 do_div(exval, rate >> fpc->period.clk_ps);
128 static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
137 c = clk_get_rate(fpc->clk[index]);
155 static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
163 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
168 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
169 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
179 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
183 return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
186 static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
191 unsigned int period = fpc->period.mod_period + 1;
192 unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
200 static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
205 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
212 static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
217 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
224 static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
234 if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
235 dev_err(fpc->chip.dev, "failed to calculate new period\n");
239 if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
247 else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
248 if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
249 dev_err(fpc->chip.dev,
254 if (fpc->period.clk_select != periodcfg.clk_select) {
256 enum fsl_pwm_clk oldclk = fpc->period.clk_select;
259 ret = clk_prepare_enable(fpc->clk[newclk]);
262 clk_disable_unprepare(fpc->clk[oldclk]);
267 ftm_clear_write_protection(fpc);
270 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
272 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
274 regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
276 fpc->period = periodcfg;
279 duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
281 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
283 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
289 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
291 ftm_set_write_protection(fpc);
299 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
312 mutex_lock(&fpc->lock);
316 regmap_set_bits(fpc->regmap, FTM_OUTMASK,
318 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
319 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
325 ret = fsl_pwm_apply_config(fpc, pwm, newstate);
331 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
335 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
337 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
341 regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
345 mutex_unlock(&fpc->lock);
356 static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
360 ret = clk_prepare_enable(fpc->ipg_clk);
364 regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
365 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
366 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
368 clk_disable_unprepare(fpc->ipg_clk);
396 struct fsl_pwm_chip *fpc;
400 fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
401 if (!fpc)
404 mutex_init(&fpc->lock);
406 fpc->soc = of_device_get_match_data(&pdev->dev);
407 fpc->chip.dev = &pdev->dev;
413 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
415 if (IS_ERR(fpc->regmap)) {
417 return PTR_ERR(fpc->regmap);
420 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
421 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
423 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
426 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
427 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
428 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
430 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
431 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
432 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
434 fpc->clk[FSL_PWM_CLK_CNTEN] =
435 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
436 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
437 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
443 fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
444 if (IS_ERR(fpc->ipg_clk))
445 fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
448 fpc->chip.ops = &fsl_pwm_ops;
449 fpc->chip.npwm = 8;
451 ret = devm_pwmchip_add(&pdev->dev, &fpc->chip);
457 platform_set_drvdata(pdev, fpc);
459 return fsl_pwm_init(fpc);
465 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
468 regcache_cache_only(fpc->regmap, true);
469 regcache_mark_dirty(fpc->regmap);
471 for (i = 0; i < fpc->chip.npwm; i++) {
472 struct pwm_device *pwm = &fpc->chip.pwms[i];
477 clk_disable_unprepare(fpc->ipg_clk);
482 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
483 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
491 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
494 for (i = 0; i < fpc->chip.npwm; i++) {
495 struct pwm_device *pwm = &fpc->chip.pwms[i];
500 clk_prepare_enable(fpc->ipg_clk);
505 clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
506 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
510 regcache_cache_only(fpc->regmap, false);
511 regcache_sync(fpc->regmap);