Lines Matching refs:clk_div
44 int clk_div;
46 clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
47 /* clk_div 1 - 128, maps to register values 0-127 */
48 if (clk_div > 0)
49 clk_div--;
51 return clk_div;
102 int clk_div = crc_pwm_calc_clk_div(state->period);
106 clk_div | pwm_output_enable);
129 unsigned int clk_div, clk_div_reg, duty_cycle_reg;
144 clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
147 DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);