Lines Matching defs:rate
66 unsigned long rate = clk_get_rate(pc->clk);
72 if (!rate) {
73 dev_err(pc->dev, "failed to get clock rate\n");
78 * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
80 * multiplication period * rate doesn't overflow.
84 * round(period * rate / NSEC_PER_SEC) <= U32_MAX
85 * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5
86 * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC
87 * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate
88 * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
89 * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
91 max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, rate) - 1;
97 period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * rate, NSEC_PER_SEC);
106 val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * rate, NSEC_PER_SEC);