Lines Matching refs:channel
99 static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
102 struct idt82p33 *idt82p33 = channel->idt82p33;
106 if (channel->pll_mode == mode)
109 err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
118 err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
123 channel->pll_mode = mode;
128 static int idt82p33_set_tod_trigger(struct idt82p33_channel *channel,
131 struct idt82p33 *idt82p33 = channel->idt82p33;
138 err = idt82p33_read(idt82p33, channel->dpll_tod_trigger,
151 return idt82p33_write(idt82p33, channel->dpll_tod_trigger,
155 static int idt82p33_get_extts(struct idt82p33_channel *channel,
158 struct idt82p33 *idt82p33 = channel->idt82p33;
162 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
168 if (memcmp(buf, channel->extts_tod_sts, TOD_BYTE_COUNT) == 0)
171 memcpy(channel->extts_tod_sts, buf, TOD_BYTE_COUNT);
175 if (channel->discard_next_extts) {
176 channel->discard_next_extts = false;
213 static int arm_tod_read_with_trigger(struct idt82p33_channel *channel, u8 trigger)
215 struct idt82p33 *idt82p33 = channel->idt82p33;
220 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
225 memcpy(channel->extts_tod_sts, buf, TOD_BYTE_COUNT);
227 err = idt82p33_set_tod_trigger(channel, trigger, false);
235 static int idt82p33_extts_enable(struct idt82p33_channel *channel,
246 idt82p33 = channel->idt82p33;
269 /* Use the pin configured for the channel */
270 ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->plln);
274 __func__, channel->plln);
286 err = arm_tod_read_with_trigger(&idt82p33->channel[index], trigger);
290 idt82p33->channel[index].tod_trigger = trigger;
291 idt82p33->event_channel[index] = channel;
318 err = idt82p33_get_extts(&idt82p33->channel[todn], &ts);
330 static u8 idt82p33_extts_enable_mask(struct idt82p33_channel *channel,
333 struct idt82p33 *idt82p33 = channel->idt82p33;
334 u8 trigger = channel->tod_trigger;
352 err = arm_tod_read_with_trigger(&idt82p33->channel[i], trigger);
372 static int _idt82p33_gettime(struct idt82p33_channel *channel,
375 struct idt82p33 *idt82p33 = channel->idt82p33;
383 new_mask = idt82p33_extts_enable_mask(channel, old_mask, false);
385 err = idt82p33_set_tod_trigger(channel, HW_TOD_RD_TRIG_SEL_LSB_TOD_STS,
390 channel->discard_next_extts = true;
395 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
402 idt82p33_extts_enable_mask(channel, new_mask, true);
415 static int _idt82p33_settime(struct idt82p33_channel *channel,
418 struct idt82p33 *idt82p33 = channel->idt82p33;
425 err = idt82p33_set_tod_trigger(channel, HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
430 channel->discard_next_extts = true;
447 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
456 static int _idt82p33_adjtime_immediate(struct idt82p33_channel *channel,
459 struct idt82p33 *idt82p33 = channel->idt82p33;
466 err = _idt82p33_gettime(channel, &ts);
476 err = _idt82p33_settime(channel, &ts);
481 static int _idt82p33_adjtime_internal_triggered(struct idt82p33_channel *channel,
484 struct idt82p33 *idt82p33 = channel->idt82p33;
492 err = _idt82p33_gettime(channel, &ts);
510 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg, buf, sizeof(buf));
517 schedule_delayed_work(&channel->adjtime_work, HZ);
519 return idt82p33_set_tod_trigger(channel, HW_TOD_TRIG_SEL_TOD_PPS, true);
524 struct idt82p33_channel *channel = container_of(work,
527 struct idt82p33 *idt82p33 = channel->idt82p33;
531 _idt82p33_adjtime_internal_triggered(channel, 0);
535 static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
537 struct idt82p33 *idt82p33 = channel->idt82p33;
564 err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
569 err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
591 static int idt82p33_stop_ddco(struct idt82p33_channel *channel)
595 err = _idt82p33_adjfine(channel, channel->current_freq);
599 channel->ddco = false;
604 static int idt82p33_start_ddco(struct idt82p33_channel *channel, s32 delta_ns)
606 s32 current_ppm = channel->current_freq;
625 err = _idt82p33_adjfine(channel,
631 ptp_schedule_worker(channel->ptp_clock,
633 channel->ddco = true;
639 struct idt82p33_channel *channel, s64 *overhead_ns)
641 struct idt82p33 *idt82p33 = channel->idt82p33;
655 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
672 struct idt82p33_channel *channel, s64 *overhead_ns)
674 struct idt82p33 *idt82p33 = channel->idt82p33;
688 err = idt82p33_read(idt82p33, channel->dpll_tod_trigger,
705 struct idt82p33_channel *channel)
707 struct idt82p33 *idt82p33 = channel->idt82p33;
724 channel->dpll_tod_cnfg + i,
742 struct idt82p33_channel *channel, s64 *overhead_ns)
750 err = _idt82p33_settime(channel, &ts1);
755 err = _idt82p33_gettime(channel, &ts2);
763 static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
766 struct idt82p33 *idt82p33 = channel->idt82p33;
771 err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);
779 err = idt82p33_measure_one_byte_write_overhead(channel,
785 err = idt82p33_measure_one_byte_read_overhead(channel,
791 err = idt82p33_measure_tod_write_9_byte_overhead(channel);
821 idt82p33->channel[0].output_mask = val;
824 idt82p33->channel[1].output_mask = val;
843 i, idt82p33->channel[i].output_mask);
847 static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
849 struct idt82p33 *idt82p33 = channel->idt82p33;
853 err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
862 return idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
868 struct idt82p33_channel *channel =
870 struct idt82p33 *idt82p33 = channel->idt82p33;
873 (void)idt82p33_stop_ddco(channel);
880 static int idt82p33_output_enable(struct idt82p33_channel *channel,
883 struct idt82p33 *idt82p33 = channel->idt82p33;
898 static int idt82p33_perout_enable(struct idt82p33_channel *channel,
903 return idt82p33_output_enable(channel, enable, perout->index);
906 static int idt82p33_enable_tod(struct idt82p33_channel *channel)
908 struct idt82p33 *idt82p33 = channel->idt82p33;
912 err = idt82p33_measure_tod_write_overhead(channel);
920 err = _idt82p33_settime(channel, &ts);
925 return idt82p33_sync_tod(channel, true);
930 struct idt82p33_channel *channel;
934 channel = &idt82p33->channel[i];
935 cancel_delayed_work_sync(&channel->adjtime_work);
936 if (channel->ptp_clock)
937 ptp_clock_unregister(channel->ptp_clock);
946 struct idt82p33_channel *channel =
948 struct idt82p33 *idt82p33 = channel->idt82p33;
956 err = idt82p33_perout_enable(channel, false,
963 err = idt82p33_perout_enable(channel, true,
967 err = idt82p33_extts_enable(channel, rq, on);
988 struct idt82p33_channel *channel =
990 struct idt82p33 *idt82p33 = channel->idt82p33;
1007 err = idt82p33_dpll_set_mode(channel, PLL_MODE_WPH);
1014 err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val,
1024 struct idt82p33_channel *channel =
1026 struct idt82p33 *idt82p33 = channel->idt82p33;
1029 if (channel->ddco == true)
1032 if (scaled_ppm == channel->current_freq)
1036 err = _idt82p33_adjfine(channel, scaled_ppm);
1039 channel->current_freq = scaled_ppm;
1050 struct idt82p33_channel *channel =
1052 struct idt82p33 *idt82p33 = channel->idt82p33;
1055 if (channel->ddco == true)
1061 err = idt82p33_start_ddco(channel, delta_ns);
1067 err = _idt82p33_adjtime_internal_triggered(channel, delta_ns);
1069 err = _idt82p33_adjtime_immediate(channel, delta_ns);
1081 struct idt82p33_channel *channel =
1083 struct idt82p33 *idt82p33 = channel->idt82p33;
1087 err = _idt82p33_gettime(channel, ts);
1099 struct idt82p33_channel *channel =
1101 struct idt82p33 *idt82p33 = channel->idt82p33;
1105 err = _idt82p33_settime(channel, ts);
1116 struct idt82p33_channel *channel = &idt82p33->channel[index];
1120 channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
1121 channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
1122 channel->dpll_tod_sts = DPLL1_TOD_STS;
1123 channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
1124 channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
1125 channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
1126 channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
1127 channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
1130 channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
1131 channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
1132 channel->dpll_tod_sts = DPLL2_TOD_STS;
1133 channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
1134 channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
1135 channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
1136 channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
1137 channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
1143 channel->plln = index;
1144 channel->current_freq = 0;
1145 channel->idt82p33 = idt82p33;
1146 INIT_DELAYED_WORK(&channel->adjtime_work, idt82p33_adjtime_workaround);
1202 struct idt82p33_channel *channel;
1208 channel = &idt82p33->channel[index];
1218 idt82p33_caps_init(index, &channel->caps,
1221 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
1223 if (IS_ERR(channel->ptp_clock)) {
1224 err = PTR_ERR(channel->ptp_clock);
1225 channel->ptp_clock = NULL;
1229 if (!channel->ptp_clock)
1232 err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
1240 err = idt82p33_enable_tod(channel);
1249 index, channel->ptp_clock->index);
1345 struct idt82p33_channel *channel;
1369 channel = &idt82p33->channel[i];
1370 arm_tod_read_with_trigger(channel, channel->tod_trigger);
1401 idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
1402 idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;