Lines Matching defs:trigger
129 u8 trigger, bool write)
135 if (trigger > WR_TRIG_SEL_MAX)
145 trigger = (trigger << WRITE_TRIGGER_SHIFT) |
148 trigger = (trigger << READ_TRIGGER_SHIFT) |
152 &trigger, sizeof(trigger));
167 /* Since trigger is not self clearing itself, we have to poll tod_sts */
183 static int map_ref_to_tod_trig_sel(int ref, u8 *trigger)
189 *trigger = HW_TOD_TRIG_SEL_IN12;
192 *trigger = HW_TOD_TRIG_SEL_IN13;
195 *trigger = HW_TOD_TRIG_SEL_IN14;
206 /* Treat single bit PLL masks as continuous trigger */
213 static int arm_tod_read_with_trigger(struct idt82p33_channel *channel, u8 trigger)
219 /* Remember the current tod_sts before setting the trigger */
227 err = idt82p33_set_tod_trigger(channel, trigger, false);
243 u8 trigger;
278 err = map_ref_to_tod_trig_sel(ref, &trigger);
286 err = arm_tod_read_with_trigger(&idt82p33->channel[index], trigger);
290 idt82p33->channel[index].tod_trigger = trigger;
334 u8 trigger = channel->tod_trigger;
352 err = arm_tod_read_with_trigger(&idt82p33->channel[i], trigger);
355 "%s: Arm ToD read trigger failed, err = %d",
360 /* trigger happened so we won't re-enable it */
498 /* Too close to miss next trigger, so skip it */
643 u8 trigger = 0;
656 &trigger, sizeof(trigger));
676 u8 trigger = 0;
689 &trigger, sizeof(trigger));
1364 /* trigger clears itself, so clear the mask */