Lines Matching defs:idt82p33
43 static inline int idt82p33_read(struct idt82p33 *idt82p33, u16 regaddr,
46 return regmap_bulk_read(idt82p33->regmap, regaddr, buf, count);
49 static inline int idt82p33_write(struct idt82p33 *idt82p33, u16 regaddr,
52 return regmap_bulk_write(idt82p33->regmap, regaddr, buf, count);
102 struct idt82p33 *idt82p33 = channel->idt82p33;
109 err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
118 err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
131 struct idt82p33 *idt82p33 = channel->idt82p33;
138 err = idt82p33_read(idt82p33, channel->dpll_tod_trigger,
151 return idt82p33_write(idt82p33, channel->dpll_tod_trigger,
158 struct idt82p33 *idt82p33 = channel->idt82p33;
162 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
215 struct idt82p33 *idt82p33 = channel->idt82p33;
220 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
230 dev_err(idt82p33->dev, "%s: err = %d", __func__, err);
239 struct idt82p33 *idt82p33;
246 idt82p33 = channel->idt82p33;
247 old_mask = idt82p33->extts_mask;
266 if (idt82p33->extts_mask & mask)
273 dev_err(idt82p33->dev, "%s: No valid pin found for Pll%d!\n",
281 dev_err(idt82p33->dev,
286 err = arm_tod_read_with_trigger(&idt82p33->channel[index], trigger);
289 idt82p33->extts_mask |= mask;
290 idt82p33->channel[index].tod_trigger = trigger;
291 idt82p33->event_channel[index] = channel;
292 idt82p33->extts_single_shot = is_one_shot(idt82p33->extts_mask);
297 schedule_delayed_work(&idt82p33->extts_work,
301 idt82p33->extts_mask &= ~mask;
302 idt82p33->extts_single_shot = is_one_shot(idt82p33->extts_mask);
304 if (idt82p33->extts_mask == 0)
305 cancel_delayed_work(&idt82p33->extts_work);
311 static int idt82p33_extts_check_channel(struct idt82p33 *idt82p33, u8 todn)
318 err = idt82p33_get_extts(&idt82p33->channel[todn], &ts);
320 event_channel = idt82p33->event_channel[todn];
333 struct idt82p33 *idt82p33 = channel->idt82p33;
343 cancel_delayed_work_sync(&idt82p33->extts_work);
352 err = arm_tod_read_with_trigger(&idt82p33->channel[i], trigger);
354 dev_err(idt82p33->dev,
358 err = idt82p33_extts_check_channel(idt82p33, i);
359 if (err == 0 && idt82p33->extts_single_shot)
366 schedule_delayed_work(&idt82p33->extts_work,
375 struct idt82p33 *idt82p33 = channel->idt82p33;
376 u8 old_mask = idt82p33->extts_mask;
392 if (idt82p33->calculate_overhead_flag)
393 idt82p33->start_time = ktime_get_raw();
395 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
418 struct idt82p33 *idt82p33 = channel->idt82p33;
432 if (idt82p33->calculate_overhead_flag) {
434 - ktime_to_ns(idt82p33->start_time);
438 idt82p33->calculate_overhead_flag = 0;
447 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
459 struct idt82p33 *idt82p33 = channel->idt82p33;
464 idt82p33->calculate_overhead_flag = 1;
472 now_ns += delta_ns + idt82p33->tod_write_overhead_ns;
484 struct idt82p33 *idt82p33 = channel->idt82p33;
510 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg, buf, sizeof(buf));
527 struct idt82p33 *idt82p33 = channel->idt82p33;
529 mutex_lock(idt82p33->lock);
532 mutex_unlock(idt82p33->lock);
537 struct idt82p33 *idt82p33 = channel->idt82p33;
569 err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
641 struct idt82p33 *idt82p33 = channel->idt82p33;
655 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
674 struct idt82p33 *idt82p33 = channel->idt82p33;
688 err = idt82p33_read(idt82p33, channel->dpll_tod_trigger,
707 struct idt82p33 *idt82p33 = channel->idt82p33;
715 idt82p33->tod_write_overhead_ns = 0;
723 err = idt82p33_write(idt82p33,
735 idt82p33->tod_write_overhead_ns = div_s64(total_ns,
766 struct idt82p33 *idt82p33 = channel->idt82p33;
769 idt82p33->tod_write_overhead_ns = 0;
774 dev_err(idt82p33->dev,
799 idt82p33->tod_write_overhead_ns -= trailing_overhead_ns;
804 static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33,
813 dev_err(idt82p33->dev,
817 idt82p33->pll_mask = val;
821 idt82p33->channel[0].output_mask = val;
824 idt82p33->channel[1].output_mask = val;
830 static void idt82p33_display_masks(struct idt82p33 *idt82p33)
834 dev_info(idt82p33->dev,
835 "pllmask = 0x%02x\n", idt82p33->pll_mask);
840 if (mask & idt82p33->pll_mask)
841 dev_info(idt82p33->dev,
843 i, idt82p33->channel[i].output_mask);
849 struct idt82p33 *idt82p33 = channel->idt82p33;
853 err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
862 return idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
870 struct idt82p33 *idt82p33 = channel->idt82p33;
872 mutex_lock(idt82p33->lock);
874 mutex_unlock(idt82p33->lock);
883 struct idt82p33 *idt82p33 = channel->idt82p33;
887 err = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
895 return idt82p33_write(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
908 struct idt82p33 *idt82p33 = channel->idt82p33;
915 dev_err(idt82p33->dev,
928 static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
934 channel = &idt82p33->channel[i];
948 struct idt82p33 *idt82p33 = channel->idt82p33;
951 mutex_lock(idt82p33->lock);
973 mutex_unlock(idt82p33->lock);
976 dev_err(idt82p33->dev,
990 struct idt82p33 *idt82p33 = channel->idt82p33;
1005 mutex_lock(idt82p33->lock);
1009 dev_err(idt82p33->dev,
1014 err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val,
1018 mutex_unlock(idt82p33->lock);
1026 struct idt82p33 *idt82p33 = channel->idt82p33;
1035 mutex_lock(idt82p33->lock);
1040 mutex_unlock(idt82p33->lock);
1043 dev_err(idt82p33->dev,
1052 struct idt82p33 *idt82p33 = channel->idt82p33;
1058 mutex_lock(idt82p33->lock);
1062 mutex_unlock(idt82p33->lock);
1071 mutex_unlock(idt82p33->lock);
1074 dev_err(idt82p33->dev,
1083 struct idt82p33 *idt82p33 = channel->idt82p33;
1086 mutex_lock(idt82p33->lock);
1088 mutex_unlock(idt82p33->lock);
1091 dev_err(idt82p33->dev,
1101 struct idt82p33 *idt82p33 = channel->idt82p33;
1104 mutex_lock(idt82p33->lock);
1106 mutex_unlock(idt82p33->lock);
1109 dev_err(idt82p33->dev,
1114 static int idt82p33_channel_init(struct idt82p33 *idt82p33, u32 index)
1116 struct idt82p33_channel *channel = &idt82p33->channel[index];
1145 channel->idt82p33 = idt82p33;
1200 static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
1208 channel = &idt82p33->channel[index];
1210 err = idt82p33_channel_init(idt82p33, index);
1212 dev_err(idt82p33->dev,
1234 dev_err(idt82p33->dev,
1242 dev_err(idt82p33->dev,
1248 dev_info(idt82p33->dev, "PLL%d registered as ptp%d\n",
1254 static int idt82p33_reset(struct idt82p33 *idt82p33, bool cold)
1262 err = idt82p33_read(idt82p33, REG_SOFT_RESET, &cfg, sizeof(cfg));
1264 dev_err(idt82p33->dev,
1272 err = idt82p33_write(idt82p33, REG_SOFT_RESET, &cfg, sizeof(cfg));
1274 dev_err(idt82p33->dev,
1279 static int idt82p33_load_firmware(struct idt82p33 *idt82p33)
1291 dev_info(idt82p33->dev, "requesting firmware '%s'\n", fname);
1293 err = request_firmware(&fw, fname, idt82p33->dev);
1296 dev_err(idt82p33->dev,
1301 dev_dbg(idt82p33->dev, "firmware size %zu bytes\n", fw->size);
1308 dev_err(idt82p33->dev,
1318 err = idt82p33_check_and_set_masks(idt82p33, page,
1327 err = idt82p33_write(idt82p33, REG_ADDR(page, loaddr),
1335 idt82p33_display_masks(idt82p33);
1343 struct idt82p33 *idt82p33 = container_of(work, struct idt82p33,
1350 if (idt82p33->extts_mask == 0)
1353 mutex_lock(idt82p33->lock);
1358 if ((idt82p33->extts_mask & mask) == 0)
1361 err = idt82p33_extts_check_channel(idt82p33, i);
1365 if (idt82p33->extts_single_shot) {
1366 idt82p33->extts_mask &= ~mask;
1369 channel = &idt82p33->channel[i];
1375 if (idt82p33->extts_mask)
1376 schedule_delayed_work(&idt82p33->extts_work,
1379 mutex_unlock(idt82p33->lock);
1385 struct idt82p33 *idt82p33;
1389 idt82p33 = devm_kzalloc(&pdev->dev,
1390 sizeof(struct idt82p33), GFP_KERNEL);
1391 if (!idt82p33)
1394 idt82p33->dev = &pdev->dev;
1395 idt82p33->mfd = pdev->dev.parent;
1396 idt82p33->lock = &ddata->lock;
1397 idt82p33->regmap = ddata->regmap;
1398 idt82p33->tod_write_overhead_ns = 0;
1399 idt82p33->calculate_overhead_flag = 0;
1400 idt82p33->pll_mask = DEFAULT_PLL_MASK;
1401 idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
1402 idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
1403 idt82p33->extts_mask = 0;
1404 INIT_DELAYED_WORK(&idt82p33->extts_work, idt82p33_extts_check);
1406 mutex_lock(idt82p33->lock);
1409 idt82p33_reset(idt82p33, true);
1411 err = idt82p33_load_firmware(idt82p33);
1413 dev_warn(idt82p33->dev,
1417 idt82p33_reset(idt82p33, false);
1419 if (idt82p33->pll_mask) {
1421 if (idt82p33->pll_mask & (1 << i))
1422 err = idt82p33_enable_channel(idt82p33, i);
1424 err = idt82p33_channel_init(idt82p33, i);
1426 dev_err(idt82p33->dev,
1433 dev_err(idt82p33->dev,
1438 mutex_unlock(idt82p33->lock);
1441 idt82p33_ptp_clock_unregister_all(idt82p33);
1445 platform_set_drvdata(pdev, idt82p33);
1452 struct idt82p33 *idt82p33 = platform_get_drvdata(pdev);
1454 cancel_delayed_work_sync(&idt82p33->extts_work);
1456 idt82p33_ptp_clock_unregister_all(idt82p33);