Lines Matching refs:channel
41 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
242 static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref)
244 struct idtcm *idtcm = channel->idtcm;
252 err = idtcm_write(idtcm, channel->tod_read_secondary,
259 err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,
273 static int idtcm_extts_enable(struct idtcm_channel *channel,
283 idtcm = channel->idtcm;
303 /* Use the pin configured for the channel */
304 ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->tod);
308 __func__, channel->tod);
312 err = arm_tod_read_trig_sel_refclk(&idtcm->channel[index], ref);
316 idtcm->event_channel[index] = channel;
317 idtcm->channel[index].refn = ref;
398 static int _idtcm_gettime_triggered(struct idtcm_channel *channel,
401 struct idtcm *idtcm = channel->idtcm;
407 err = idtcm_read(idtcm, channel->tod_read_secondary,
415 err = idtcm_read(idtcm, channel->tod_read_secondary,
423 static int _idtcm_gettime(struct idtcm_channel *channel,
426 struct idtcm *idtcm = channel->idtcm;
440 err = idtcm_read(idtcm, channel->tod_read_primary,
447 err = idtcm_read(idtcm, channel->tod_read_primary,
465 extts_channel = &idtcm->channel[todn];
484 static int _idtcm_gettime_immediate(struct idtcm_channel *channel,
487 struct idtcm *idtcm = channel->idtcm;
493 err = idtcm_write(idtcm, channel->tod_read_primary,
498 return _idtcm_gettime(channel, ts, 10);
628 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
630 struct idtcm *idtcm = channel->idtcm;
638 u16 output_mask = channel->output_mask;
695 err = _sync_pll_output(idtcm, pll, channel->sync_src,
705 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
709 struct idtcm *idtcm = channel->idtcm;
717 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
725 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
735 err = idtcm_write(idtcm, channel->hw_dpll_n,
744 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
765 err = idtcm_write(idtcm, channel->hw_dpll_n,
772 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
777 struct idtcm *idtcm = channel->idtcm;
788 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
794 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
804 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
815 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
881 static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
884 struct idtcm *idtcm = channel->idtcm;
887 err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
894 return idtcm_sync_pps_output(channel);
897 static int _idtcm_settime(struct idtcm_channel *channel,
901 return _idtcm_set_dpll_scsr_tod(channel, ts,
906 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
911 struct idtcm *idtcm = channel->idtcm;
919 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
925 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
930 struct idtcm *idtcm = channel->idtcm;
941 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
947 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
950 struct idtcm *idtcm = channel->idtcm;
953 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
960 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
969 static int do_phase_pull_in_fw(struct idtcm_channel *channel,
975 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
979 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
983 err = idtcm_start_phase_pull_in(channel);
988 static int set_tod_write_overhead(struct idtcm_channel *channel)
990 struct idtcm *idtcm = channel->idtcm;
1002 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
1008 err = idtcm_write(idtcm, channel->hw_dpll_n,
1032 static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
1035 struct idtcm *idtcm = channel->idtcm;
1040 err = channel->do_phase_pull_in(channel, delta, 0);
1044 err = set_tod_write_overhead(channel);
1048 err = _idtcm_gettime_immediate(channel, &ts);
1057 err = _idtcm_settime_deprecated(channel, &ts);
1152 SET_U16_LSB(idtcm->channel[0].output_mask, val);
1155 SET_U16_MSB(idtcm->channel[0].output_mask, val);
1158 SET_U16_LSB(idtcm->channel[1].output_mask, val);
1161 SET_U16_MSB(idtcm->channel[1].output_mask, val);
1164 SET_U16_LSB(idtcm->channel[2].output_mask, val);
1167 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1170 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1173 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1195 idtcm->channel[index].pll = pll;
1248 i, idtcm->channel[i].pll,
1249 idtcm->channel[i].output_mask);
1327 static int idtcm_output_enable(struct idtcm_channel *channel,
1330 struct idtcm *idtcm = channel->idtcm;
1355 static int idtcm_perout_enable(struct idtcm_channel *channel,
1359 struct idtcm *idtcm = channel->idtcm;
1363 err = idtcm_output_enable(channel, enable, perout->index);
1371 return _idtcm_settime(channel, &ts, SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS);
1374 static int idtcm_get_pll_mode(struct idtcm_channel *channel,
1377 struct idtcm *idtcm = channel->idtcm;
1381 err = idtcm_read(idtcm, channel->dpll_n,
1392 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1395 struct idtcm *idtcm = channel->idtcm;
1399 err = idtcm_read(idtcm, channel->dpll_n,
1409 err = idtcm_write(idtcm, channel->dpll_n,
1415 static int idtcm_get_manual_reference(struct idtcm_channel *channel,
1418 struct idtcm *idtcm = channel->idtcm;
1422 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1435 static int idtcm_set_manual_reference(struct idtcm_channel *channel,
1438 struct idtcm *idtcm = channel->idtcm;
1442 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1452 err = idtcm_write(idtcm, channel->dpll_ctrl_n,
1459 static int configure_dpll_mode_write_frequency(struct idtcm_channel *channel)
1461 struct idtcm *idtcm = channel->idtcm;
1464 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1469 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1474 static int configure_dpll_mode_write_phase(struct idtcm_channel *channel)
1476 struct idtcm *idtcm = channel->idtcm;
1479 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1484 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1489 static int configure_manual_reference_write_frequency(struct idtcm_channel *channel)
1491 struct idtcm *idtcm = channel->idtcm;
1494 err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_FREQUENCY);
1499 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1504 static int configure_manual_reference_write_phase(struct idtcm_channel *channel)
1506 struct idtcm *idtcm = channel->idtcm;
1509 err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_PHASE);
1514 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1519 static int idtcm_stop_phase_pull_in(struct idtcm_channel *channel)
1523 err = _idtcm_adjfine(channel, channel->current_freq_scaled_ppm);
1527 channel->phase_pull_in = false;
1534 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1535 struct idtcm *idtcm = channel->idtcm;
1539 (void)idtcm_stop_phase_pull_in(channel);
1565 static int do_phase_pull_in_sw(struct idtcm_channel *channel,
1569 s32 current_ppm = channel->current_freq_scaled_ppm;
1594 err = _idtcm_adjfine(channel, delta_ppm);
1600 ptp_schedule_worker(channel->ptp_clock,
1603 channel->phase_pull_in = true;
1608 static int initialize_operating_mode_with_manual_reference(struct idtcm_channel *channel,
1611 struct idtcm *idtcm = channel->idtcm;
1613 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1614 channel->configure_write_frequency = configure_manual_reference_write_frequency;
1615 channel->configure_write_phase = configure_manual_reference_write_phase;
1616 channel->do_phase_pull_in = do_phase_pull_in_sw;
1620 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1623 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1633 static int initialize_operating_mode_with_pll_mode(struct idtcm_channel *channel,
1636 struct idtcm *idtcm = channel->idtcm;
1639 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1640 channel->configure_write_frequency = configure_dpll_mode_write_frequency;
1641 channel->configure_write_phase = configure_dpll_mode_write_phase;
1642 channel->do_phase_pull_in = do_phase_pull_in_fw;
1646 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1649 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1660 static int initialize_dco_operating_mode(struct idtcm_channel *channel)
1664 struct idtcm *idtcm = channel->idtcm;
1667 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1669 err = idtcm_get_pll_mode(channel, &mode);
1676 err = idtcm_get_manual_reference(channel, &ref);
1681 err = initialize_operating_mode_with_manual_reference(channel, ref);
1683 err = initialize_operating_mode_with_pll_mode(channel, mode);
1686 if (channel->mode == PTP_PLL_MODE_WRITE_PHASE)
1687 channel->configure_write_frequency(channel);
1710 * @channel: channel
1713 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1715 struct idtcm *idtcm = channel->idtcm;
1721 if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
1722 err = channel->configure_write_phase(channel);
1734 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1740 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1742 struct idtcm *idtcm = channel->idtcm;
1748 if (channel->mode != PTP_PLL_MODE_WRITE_FREQUENCY) {
1749 err = channel->configure_write_frequency(channel);
1778 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1786 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1787 struct idtcm *idtcm = channel->idtcm;
1791 err = _idtcm_gettime_immediate(channel, ts);
1804 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1805 struct idtcm *idtcm = channel->idtcm;
1809 err = _idtcm_settime_deprecated(channel, ts);
1822 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1823 struct idtcm *idtcm = channel->idtcm;
1827 err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1839 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1840 struct idtcm *idtcm = channel->idtcm;
1844 err = _idtcm_adjtime_deprecated(channel, delta);
1856 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1857 struct idtcm *idtcm = channel->idtcm;
1862 if (channel->phase_pull_in == true)
1868 err = channel->do_phase_pull_in(channel, delta, 0);
1877 err = _idtcm_settime(channel, &ts, type);
1891 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1892 struct idtcm *idtcm = channel->idtcm;
1896 err = _idtcm_adjphase(channel, delta);
1908 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1909 struct idtcm *idtcm = channel->idtcm;
1912 if (channel->phase_pull_in == true)
1915 if (scaled_ppm == channel->current_freq_scaled_ppm)
1919 err = _idtcm_adjfine(channel, scaled_ppm);
1926 channel->current_freq_scaled_ppm = scaled_ppm;
1934 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1935 struct idtcm *idtcm = channel->idtcm;
1943 err = idtcm_perout_enable(channel, &rq->perout, false);
1949 err = idtcm_perout_enable(channel, &rq->perout, true);
1952 err = idtcm_extts_enable(channel, rq, on);
1961 dev_err(channel->idtcm->dev,
1967 static int idtcm_enable_tod(struct idtcm_channel *channel)
1969 struct idtcm *idtcm = channel->idtcm;
1978 err = idtcm_read(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
1984 err = idtcm_write(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
1989 return _idtcm_settime_deprecated(channel, &ts);
1991 return _idtcm_settime(channel, &ts,
2074 static int configure_channel_pll(struct idtcm_channel *channel)
2076 struct idtcm *idtcm = channel->idtcm;
2079 switch (channel->pll) {
2081 channel->dpll_freq = DPLL_FREQ_0;
2082 channel->dpll_n = DPLL_0;
2083 channel->hw_dpll_n = HW_DPLL_0;
2084 channel->dpll_phase = DPLL_PHASE_0;
2085 channel->dpll_ctrl_n = DPLL_CTRL_0;
2086 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
2089 channel->dpll_freq = DPLL_FREQ_1;
2090 channel->dpll_n = DPLL_1;
2091 channel->hw_dpll_n = HW_DPLL_1;
2092 channel->dpll_phase = DPLL_PHASE_1;
2093 channel->dpll_ctrl_n = DPLL_CTRL_1;
2094 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
2097 channel->dpll_freq = DPLL_FREQ_2;
2098 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_2);
2099 channel->hw_dpll_n = HW_DPLL_2;
2100 channel->dpll_phase = DPLL_PHASE_2;
2101 channel->dpll_ctrl_n = DPLL_CTRL_2;
2102 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
2105 channel->dpll_freq = DPLL_FREQ_3;
2106 channel->dpll_n = DPLL_3;
2107 channel->hw_dpll_n = HW_DPLL_3;
2108 channel->dpll_phase = DPLL_PHASE_3;
2109 channel->dpll_ctrl_n = DPLL_CTRL_3;
2110 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
2113 channel->dpll_freq = DPLL_FREQ_4;
2114 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_4);
2115 channel->hw_dpll_n = HW_DPLL_4;
2116 channel->dpll_phase = DPLL_PHASE_4;
2117 channel->dpll_ctrl_n = DPLL_CTRL_4;
2118 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
2121 channel->dpll_freq = DPLL_FREQ_5;
2122 channel->dpll_n = DPLL_5;
2123 channel->hw_dpll_n = HW_DPLL_5;
2124 channel->dpll_phase = DPLL_PHASE_5;
2125 channel->dpll_ctrl_n = DPLL_CTRL_5;
2126 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
2129 channel->dpll_freq = DPLL_FREQ_6;
2130 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_6);
2131 channel->hw_dpll_n = HW_DPLL_6;
2132 channel->dpll_phase = DPLL_PHASE_6;
2133 channel->dpll_ctrl_n = DPLL_CTRL_6;
2134 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
2137 channel->dpll_freq = DPLL_FREQ_7;
2138 channel->dpll_n = DPLL_7;
2139 channel->hw_dpll_n = HW_DPLL_7;
2140 channel->dpll_phase = DPLL_PHASE_7;
2141 channel->dpll_ctrl_n = DPLL_CTRL_7;
2142 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
2155 static u32 idtcm_get_dco_delay(struct idtcm_channel *channel)
2157 struct idtcm *idtcm = channel->idtcm;
2165 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2170 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2189 static int configure_channel_tod(struct idtcm_channel *channel, u32 index)
2191 enum fw_version fw_ver = channel->idtcm->fw_ver;
2196 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_0);
2197 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_0);
2198 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_0);
2199 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_0);
2200 channel->sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
2203 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_1);
2204 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_1);
2205 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_1);
2206 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_1);
2207 channel->sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
2210 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_2);
2211 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_2);
2212 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_2);
2213 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_2);
2214 channel->sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
2217 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_3);
2218 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_3);
2219 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_3);
2220 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_3);
2221 channel->sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
2232 struct idtcm_channel *channel;
2239 channel = &idtcm->channel[index];
2241 channel->idtcm = idtcm;
2242 channel->current_freq_scaled_ppm = 0;
2245 err = configure_channel_pll(channel);
2250 err = configure_channel_tod(channel, index);
2255 channel->caps = idtcm_caps_deprecated;
2257 channel->caps = idtcm_caps;
2259 snprintf(channel->caps.name, sizeof(channel->caps.name),
2262 channel->caps.pin_config = pin_config[index];
2264 for (i = 0; i < channel->caps.n_pins; ++i) {
2265 struct ptp_pin_desc *ppd = &channel->caps.pin_config[i];
2273 err = initialize_dco_operating_mode(channel);
2277 err = idtcm_enable_tod(channel);
2284 channel->dco_delay = idtcm_get_dco_delay(channel);
2286 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2288 if (IS_ERR(channel->ptp_clock)) {
2289 err = PTR_ERR(channel->ptp_clock);
2290 channel->ptp_clock = NULL;
2294 if (!channel->ptp_clock)
2298 index, channel->ptp_clock->index);
2305 struct idtcm_channel *channel;
2311 channel = &idtcm->channel[index];
2312 channel->idtcm = idtcm;
2315 err = configure_channel_tod(channel, index);
2319 channel->idtcm = idtcm;
2327 struct idtcm_channel *channel;
2351 channel = &idtcm->channel[i];
2352 arm_tod_read_trig_sel_refclk(channel, channel->refn);
2367 struct idtcm_channel *channel;
2370 channel = &idtcm->channel[i];
2371 if (channel->ptp_clock)
2372 ptp_clock_unregister(channel->ptp_clock);
2381 idtcm->channel[0].tod = 0;
2382 idtcm->channel[1].tod = 1;
2383 idtcm->channel[2].tod = 2;
2384 idtcm->channel[3].tod = 3;
2386 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2387 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2388 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2389 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2391 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2392 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2393 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2394 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;