Lines Matching defs:mode
1375 enum pll_mode *mode)
1387 *mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
1393 enum pll_mode mode)
1407 dpll_mode |= (mode << PLL_MODE_SHIFT);
1467 dev_err(idtcm->dev, "Failed to set pll mode to write frequency");
1469 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1482 dev_err(idtcm->dev, "Failed to set pll mode to write phase");
1484 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1499 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1514 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1613 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1620 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1623 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1634 enum pll_mode mode)
1639 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1644 switch (mode) {
1646 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1649 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1653 "Unsupported PLL_MODE: 0x%02x", mode);
1663 enum pll_mode mode = PLL_MODE_DISABLED;
1667 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1669 err = idtcm_get_pll_mode(channel, &mode);
1671 dev_err(idtcm->dev, "Unable to read pll mode!");
1675 if (mode == PLL_MODE_PLL) {
1683 err = initialize_operating_mode_with_pll_mode(channel, mode);
1686 if (channel->mode == PTP_PLL_MODE_WRITE_PHASE)
1721 if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
1748 if (channel->mode != PTP_PLL_MODE_WRITE_FREQUENCY) {