Lines Matching defs:idtcm
43 static inline int idtcm_read(struct idtcm *idtcm,
49 return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count);
52 static inline int idtcm_write(struct idtcm *idtcm,
58 return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count);
61 static int contains_full_configuration(struct idtcm *idtcm,
65 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
199 static int clear_boot_status(struct idtcm *idtcm)
203 return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
206 static int read_boot_status(struct idtcm *idtcm, u32 *status)
211 err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
218 static int wait_for_boot_status_ready(struct idtcm *idtcm)
225 err = read_boot_status(idtcm, &status);
237 dev_warn(idtcm->dev, "%s timed out", __func__);
244 struct idtcm *idtcm = channel->idtcm;
245 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
252 err = idtcm_write(idtcm, channel->tod_read_secondary,
259 err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,
262 dev_err(idtcm->dev, "%s: err = %d", __func__, err);
277 struct idtcm *idtcm;
283 idtcm = channel->idtcm;
284 old_mask = idtcm->extts_mask;
307 dev_err(idtcm->dev, "%s: No valid pin found for TOD%d!\n",
312 err = arm_tod_read_trig_sel_refclk(&idtcm->channel[index], ref);
315 idtcm->extts_mask |= mask;
316 idtcm->event_channel[index] = channel;
317 idtcm->channel[index].refn = ref;
318 idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
323 schedule_delayed_work(&idtcm->extts_work,
327 idtcm->extts_mask &= ~mask;
328 idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
330 if (idtcm->extts_mask == 0)
331 cancel_delayed_work(&idtcm->extts_work);
337 static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
339 return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status,
343 static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status)
345 return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8));
348 static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
356 err = read_sys_apll_status(idtcm, &apll);
360 err = read_sys_dpll_status(idtcm, &dpll);
373 dev_warn(idtcm->dev,
381 dev_warn(idtcm->dev,
388 static void wait_for_chip_ready(struct idtcm *idtcm)
390 if (wait_for_boot_status_ready(idtcm))
391 dev_warn(idtcm->dev, "BOOT_STATUS != 0xA0");
393 if (wait_for_sys_apll_dpll_lock(idtcm))
394 dev_warn(idtcm->dev,
401 struct idtcm *idtcm = channel->idtcm;
402 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
407 err = idtcm_read(idtcm, channel->tod_read_secondary,
415 err = idtcm_read(idtcm, channel->tod_read_secondary,
426 struct idtcm *idtcm = channel->idtcm;
427 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
437 if (idtcm->calculate_overhead_flag)
438 idtcm->start_time = ktime_get_raw();
440 err = idtcm_read(idtcm, channel->tod_read_primary,
447 err = idtcm_read(idtcm, channel->tod_read_primary,
457 static int idtcm_extts_check_channel(struct idtcm *idtcm, u8 todn)
465 extts_channel = &idtcm->channel[todn];
466 ptp_channel = idtcm->event_channel[todn];
487 struct idtcm *idtcm = channel->idtcm;
489 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
493 err = idtcm_write(idtcm, channel->tod_read_primary,
501 static int _sync_pll_output(struct idtcm *idtcm,
556 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
560 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
573 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
579 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
586 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
593 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
601 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
608 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
615 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
623 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
630 struct idtcm *idtcm = channel->idtcm;
640 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
649 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
695 err = _sync_pll_output(idtcm, pll, channel->sync_src,
709 struct idtcm *idtcm = channel->idtcm;
717 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
725 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
735 err = idtcm_write(idtcm, channel->hw_dpll_n,
744 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
748 if (idtcm->calculate_overhead_flag) {
751 idtcm->start_time);
753 + idtcm->tod_write_overhead_ns
758 idtcm->calculate_overhead_flag = 0;
765 err = idtcm_write(idtcm, channel->hw_dpll_n,
777 struct idtcm *idtcm = channel->idtcm;
788 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
794 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
804 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
815 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
824 dev_err(idtcm->dev,
884 struct idtcm *idtcm = channel->idtcm;
889 dev_err(idtcm->dev,
911 struct idtcm *idtcm = channel->idtcm;
919 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
930 struct idtcm *idtcm = channel->idtcm;
941 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
950 struct idtcm *idtcm = channel->idtcm;
953 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
960 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
990 struct idtcm *idtcm = channel->idtcm;
1002 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
1008 err = idtcm_write(idtcm, channel->hw_dpll_n,
1027 idtcm->tod_write_overhead_ns = lowest_ns;
1035 struct idtcm *idtcm = channel->idtcm;
1042 idtcm->calculate_overhead_flag = 1;
1063 static int idtcm_state_machine_reset(struct idtcm *idtcm)
1070 clear_boot_status(idtcm);
1072 err = idtcm_write(idtcm, RESET_CTRL,
1073 IDTCM_FW_REG(idtcm->fw_ver, V520, SM_RESET),
1079 read_boot_status(idtcm, &status);
1082 dev_dbg(idtcm->dev,
1089 dev_err(idtcm->dev,
1096 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
1098 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
1101 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
1106 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
1113 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
1118 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
1125 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
1127 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
1130 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
1132 return idtcm_read(idtcm,
1139 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
1142 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
1146 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
1152 SET_U16_LSB(idtcm->channel[0].output_mask, val);
1155 SET_U16_MSB(idtcm->channel[0].output_mask, val);
1158 SET_U16_LSB(idtcm->channel[1].output_mask, val);
1161 SET_U16_MSB(idtcm->channel[1].output_mask, val);
1164 SET_U16_LSB(idtcm->channel[2].output_mask, val);
1167 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1170 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1173 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1183 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1186 dev_err(idtcm->dev, "ToD%d not supported", index);
1191 dev_err(idtcm->dev, "Pll%d not supported", pll);
1195 idtcm->channel[index].pll = pll;
1200 static int check_and_set_masks(struct idtcm *idtcm,
1209 dev_err(idtcm->dev, "Invalid TOD mask 0x%02x", val);
1212 idtcm->tod_mask = val;
1216 err = set_tod_ptp_pll(idtcm, 0, val);
1219 err = set_tod_ptp_pll(idtcm, 1, val);
1222 err = set_tod_ptp_pll(idtcm, 2, val);
1225 err = set_tod_ptp_pll(idtcm, 3, val);
1228 err = set_pll_output_mask(idtcm, regaddr, val);
1235 static void display_pll_and_masks(struct idtcm *idtcm)
1240 dev_dbg(idtcm->dev, "tod_mask = 0x%02x", idtcm->tod_mask);
1245 if (mask & idtcm->tod_mask)
1246 dev_dbg(idtcm->dev,
1248 i, idtcm->channel[i].pll,
1249 idtcm->channel[i].output_mask);
1253 static int idtcm_load_firmware(struct idtcm *idtcm,
1256 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
1269 dev_info(idtcm->dev, "requesting firmware '%s'", fname);
1273 dev_err(idtcm->dev,
1278 dev_dbg(idtcm->dev, "firmware size %zu bytes", fw->size);
1282 if (contains_full_configuration(idtcm, fw))
1283 idtcm_state_machine_reset(idtcm);
1287 dev_err(idtcm->dev,
1299 err = check_and_set_masks(idtcm, regaddr, val);
1313 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1320 display_pll_and_masks(idtcm);
1330 struct idtcm *idtcm = channel->idtcm;
1335 base = get_output_base_addr(idtcm->fw_ver, outn);
1338 dev_err(idtcm->dev,
1343 err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1352 return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1359 struct idtcm *idtcm = channel->idtcm;
1366 dev_err(idtcm->dev, "Unable to set output enable");
1377 struct idtcm *idtcm = channel->idtcm;
1381 err = idtcm_read(idtcm, channel->dpll_n,
1382 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1395 struct idtcm *idtcm = channel->idtcm;
1399 err = idtcm_read(idtcm, channel->dpll_n,
1400 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1409 err = idtcm_write(idtcm, channel->dpll_n,
1410 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1418 struct idtcm *idtcm = channel->idtcm;
1422 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1438 struct idtcm *idtcm = channel->idtcm;
1442 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1452 err = idtcm_write(idtcm, channel->dpll_ctrl_n,
1461 struct idtcm *idtcm = channel->idtcm;
1467 dev_err(idtcm->dev, "Failed to set pll mode to write frequency");
1476 struct idtcm *idtcm = channel->idtcm;
1482 dev_err(idtcm->dev, "Failed to set pll mode to write phase");
1491 struct idtcm *idtcm = channel->idtcm;
1497 dev_err(idtcm->dev, "Failed to set manual reference to write frequency");
1506 struct idtcm *idtcm = channel->idtcm;
1512 dev_err(idtcm->dev, "Failed to set manual reference to write phase");
1535 struct idtcm *idtcm = channel->idtcm;
1537 mutex_lock(idtcm->lock);
1541 mutex_unlock(idtcm->lock);
1611 struct idtcm *idtcm = channel->idtcm;
1626 dev_warn(idtcm->dev,
1636 struct idtcm *idtcm = channel->idtcm;
1652 dev_err(idtcm->dev,
1664 struct idtcm *idtcm = channel->idtcm;
1671 dev_err(idtcm->dev, "Unable to read pll mode!");
1678 dev_err(idtcm->dev, "Unable to read manual reference!");
1715 struct idtcm *idtcm = channel->idtcm;
1734 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1742 struct idtcm *idtcm = channel->idtcm;
1778 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1787 struct idtcm *idtcm = channel->idtcm;
1790 mutex_lock(idtcm->lock);
1792 mutex_unlock(idtcm->lock);
1795 dev_err(idtcm->dev, "Failed at line %d in %s!",
1805 struct idtcm *idtcm = channel->idtcm;
1808 mutex_lock(idtcm->lock);
1810 mutex_unlock(idtcm->lock);
1813 dev_err(idtcm->dev,
1823 struct idtcm *idtcm = channel->idtcm;
1826 mutex_lock(idtcm->lock);
1828 mutex_unlock(idtcm->lock);
1831 dev_err(idtcm->dev,
1840 struct idtcm *idtcm = channel->idtcm;
1843 mutex_lock(idtcm->lock);
1845 mutex_unlock(idtcm->lock);
1848 dev_err(idtcm->dev,
1857 struct idtcm *idtcm = channel->idtcm;
1865 mutex_lock(idtcm->lock);
1880 mutex_unlock(idtcm->lock);
1883 dev_err(idtcm->dev,
1892 struct idtcm *idtcm = channel->idtcm;
1895 mutex_lock(idtcm->lock);
1897 mutex_unlock(idtcm->lock);
1900 dev_err(idtcm->dev,
1909 struct idtcm *idtcm = channel->idtcm;
1918 mutex_lock(idtcm->lock);
1920 mutex_unlock(idtcm->lock);
1923 dev_err(idtcm->dev,
1935 struct idtcm *idtcm = channel->idtcm;
1938 mutex_lock(idtcm->lock);
1958 mutex_unlock(idtcm->lock);
1961 dev_err(channel->idtcm->dev,
1969 struct idtcm *idtcm = channel->idtcm;
1971 u16 tod_cfg = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_CFG);
1978 err = idtcm_read(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
1984 err = idtcm_write(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
1988 if (idtcm->fw_ver < V487)
1995 static void idtcm_set_version_info(struct idtcm *idtcm)
2004 idtcm_read_major_release(idtcm, &major);
2005 idtcm_read_minor_release(idtcm, &minor);
2006 idtcm_read_hotfix_release(idtcm, &hotfix);
2008 idtcm_read_product_id(idtcm, &product_id);
2009 idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
2011 idtcm_read_otp_scsr_config_select(idtcm, &config_select);
2013 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
2016 idtcm->fw_ver = idtcm_fw_version(idtcm->version);
2018 dev_info(idtcm->dev,
2076 struct idtcm *idtcm = channel->idtcm;
2098 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_2);
2114 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_4);
2130 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_6);
2157 struct idtcm *idtcm = channel->idtcm;
2165 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2170 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2191 enum fw_version fw_ver = channel->idtcm->fw_ver;
2230 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
2239 channel = &idtcm->channel[index];
2241 channel->idtcm = idtcm;
2254 if (idtcm->fw_ver < V487)
2279 dev_err(idtcm->dev,
2297 dev_info(idtcm->dev, "PLL%d registered as ptp%d",
2303 static int idtcm_enable_extts_channel(struct idtcm *idtcm, u32 index)
2311 channel = &idtcm->channel[index];
2312 channel->idtcm = idtcm;
2319 channel->idtcm = idtcm;
2326 struct idtcm *idtcm = container_of(work, struct idtcm, extts_work.work);
2332 if (idtcm->extts_mask == 0)
2335 mutex_lock(idtcm->lock);
2340 if ((idtcm->extts_mask & mask) == 0)
2343 err = idtcm_extts_check_channel(idtcm, i);
2347 if (idtcm->extts_single_shot) {
2348 idtcm->extts_mask &= ~mask;
2351 channel = &idtcm->channel[i];
2357 if (idtcm->extts_mask)
2358 schedule_delayed_work(&idtcm->extts_work,
2361 mutex_unlock(idtcm->lock);
2364 static void ptp_clock_unregister_all(struct idtcm *idtcm)
2370 channel = &idtcm->channel[i];
2376 static void set_default_masks(struct idtcm *idtcm)
2378 idtcm->tod_mask = DEFAULT_TOD_MASK;
2379 idtcm->extts_mask = 0;
2381 idtcm->channel[0].tod = 0;
2382 idtcm->channel[1].tod = 1;
2383 idtcm->channel[2].tod = 2;
2384 idtcm->channel[3].tod = 3;
2386 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2387 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2388 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2389 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2391 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2392 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2393 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2394 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2400 struct idtcm *idtcm;
2404 idtcm = devm_kzalloc(&pdev->dev, sizeof(struct idtcm), GFP_KERNEL);
2406 if (!idtcm)
2409 idtcm->dev = &pdev->dev;
2410 idtcm->mfd = pdev->dev.parent;
2411 idtcm->lock = &ddata->lock;
2412 idtcm->regmap = ddata->regmap;
2413 idtcm->calculate_overhead_flag = 0;
2415 INIT_DELAYED_WORK(&idtcm->extts_work, idtcm_extts_check);
2417 set_default_masks(idtcm);
2419 mutex_lock(idtcm->lock);
2421 idtcm_set_version_info(idtcm);
2423 err = idtcm_load_firmware(idtcm, &pdev->dev);
2426 dev_warn(idtcm->dev, "loading firmware failed with %d", err);
2428 wait_for_chip_ready(idtcm);
2430 if (idtcm->tod_mask) {
2432 if (idtcm->tod_mask & (1 << i))
2433 err = idtcm_enable_channel(idtcm, i);
2435 err = idtcm_enable_extts_channel(idtcm, i);
2437 dev_err(idtcm->dev,
2443 dev_err(idtcm->dev,
2448 mutex_unlock(idtcm->lock);
2451 ptp_clock_unregister_all(idtcm);
2455 platform_set_drvdata(pdev, idtcm);
2462 struct idtcm *idtcm = platform_get_drvdata(pdev);
2464 idtcm->extts_mask = 0;
2465 ptp_clock_unregister_all(idtcm);
2466 cancel_delayed_work_sync(&idtcm->extts_work);