Lines Matching refs:regmap

17 #include <linux/regmap.h>
42 	struct regmap *regmap;
90 	struct regmap *regmap;
104 	regmap_update_bits(clk->regmap, GPR_REG2,
111 	regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST, PLL_RST);
114 	regmap_update_bits(clk->regmap, GPR_REG3, PLL_CKE, PLL_CKE);
116 	return regmap_read_poll_timeout(clk->regmap, GPR_REG1, val,
124 	regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST | PLL_CKE, 0);
131 	return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK);
163 	clk_hsio_pll->regmap = bc->regmap;
179 		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
182 		regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
185 		regmap_set_bits(bc->regmap, GPR_REG0,
198 		regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
201 		regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
204 		regmap_clear_bits(bc->regmap, GPR_REG0,
230 		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
234 		regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
243 		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
310 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
311 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
314 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
317 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
318 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
320 		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0,
324 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
325 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
328 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
329 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
332 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
333 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
336 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
338 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
341 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
343 		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
346 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
347 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
348 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
349 		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
352 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
355 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
356 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
368 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
369 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
372 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
374 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
375 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
380 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
381 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
384 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
385 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
388 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
389 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
392 		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
393 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
395 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
398 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
402 		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
403 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
404 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
405 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
408 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
411 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
412 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
434 	regmap_write(bc->regmap, HDMI_RTX_RESET_CTL0, 0x0);
435 	regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0);
436 	regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);
437 	regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
439 	regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));
627 	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
628 	if (IS_ERR(bc->regmap))
629 		return dev_err_probe(dev, PTR_ERR(bc->regmap),
630 				     "failed to init regmap\n");