Lines Matching refs:REG_PINMUX5
24 #define REG_PINMUX5 0x3010
171 VISCONTI_PIN_GROUP(i2c7, REG_PINMUX5, GENMASK(23, 20), 0x00200000),
172 VISCONTI_PIN_GROUP(i2c8, REG_PINMUX5, GENMASK(31, 24), 0x22000000),
173 VISCONTI_PIN_GROUP(spi0_cs0, REG_PINMUX5, GENMASK(23, 20), 0x00100000),
174 VISCONTI_PIN_GROUP(spi0_cs1, REG_PINMUX5, GENMASK(27, 24), 0x01000000),
175 VISCONTI_PIN_GROUP(spi0_cs2, REG_PINMUX5, GENMASK(31, 28), 0x10000000),
181 VISCONTI_PIN_GROUP(spi6_cs, REG_PINMUX5, GENMASK(15, 12), 0x00001000),
188 VISCONTI_PIN_GROUP(spi6, REG_PINMUX5, GENMASK(11, 0), 0x00000111),
210 VISCONTI_PIN_GROUP(pcmif_in, REG_PINMUX5, GENMASK(11, 0), 0x00000222),
305 tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(3, 0)),
306 tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(7, 4)),
307 tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(11, 8)),
308 tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(15, 12)),
309 tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(19, 16)),
310 tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(23, 20)),
311 tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(27, 24)),
312 tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(31, 28)),