Lines Matching defs:REG_PINMUX4
23 #define REG_PINMUX4 0x300c
168 VISCONTI_PIN_GROUP(i2c4, REG_PINMUX4, GENMASK(7, 0), 0x00000077),
169 VISCONTI_PIN_GROUP(i2c5, REG_PINMUX4, GENMASK(15, 8), 0x00007700),
179 VISCONTI_PIN_GROUP(spi4_cs, REG_PINMUX4, GENMASK(31, 28), 0x10000000),
180 VISCONTI_PIN_GROUP(spi5_cs, REG_PINMUX4, GENMASK(15, 12), 0x00001000),
187 VISCONTI_PIN_GROUP(spi5, REG_PINMUX4, GENMASK(11, 0), 0x00000111),
192 VISCONTI_PIN_GROUP(uart3, REG_PINMUX4, GENMASK(15, 0), 0x00002222),
205 VISCONTI_PIN_GROUP(pwm0_gpio16, REG_PINMUX4, GENMASK(3, 0), 0x00000005),
206 VISCONTI_PIN_GROUP(pwm1_gpio17, REG_PINMUX4, GENMASK(7, 4), 0x00000050),
207 VISCONTI_PIN_GROUP(pwm2_gpio18, REG_PINMUX4, GENMASK(11, 8), 0x00000500),
208 VISCONTI_PIN_GROUP(pwm3_gpio19, REG_PINMUX4, GENMASK(15, 12), 0x00005000),
209 VISCONTI_PIN_GROUP(pcmif_out, REG_PINMUX4, GENMASK(27, 16), 0x01110000),
297 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(3, 0)),
298 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(7, 4)),
299 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(11, 8)),
300 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(15, 12)),
301 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(19, 16)),
302 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(23, 20)),
303 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(27, 24)),
304 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(31, 28)),