Lines Matching defs:pmx

30 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
32 	return readl(pmx->regs[bank] + reg);
35 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
37 	writel_relaxed(val, pmx->regs[bank] + reg);
39 	pmx_readl(pmx, bank, reg);
44 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
46 	return pmx->soc->ngroups;
52 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
54 	return pmx->soc->groups[group].name;
62 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
64 	*pins = pmx->soc->groups[group].pins;
65 	*num_pins = pmx->soc->groups[group].npins;
225 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
227 	return pmx->soc->nfunctions;
233 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
235 	return pmx->functions[function].name;
243 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
245 	*groups = pmx->functions[function].groups;
246 	*num_groups = pmx->functions[function].ngroups;
255 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
260 	g = &pmx->soc->groups[group];
272 	val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
275 	pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
283 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
288 	for (group = 0; group < pmx->soc->ngroups; ++group) {
294 				return &pmx->soc->groups[group];
306 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
310 	if (!pmx->soc->sfsel_in_mux)
321 	value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
323 	pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
332 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
336 	if (!pmx->soc->sfsel_in_mux)
347 	value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
349 	pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
361 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
411 		if (pmx->soc->hsm_in_mux) {
422 		if (pmx->soc->schmitt_in_mux) {
463 		if (pmx->soc->drvtype_in_mux) {
474 		dev_err(pmx->dev, "Invalid config param %04x\n", param);
490 			dev_err(pmx->dev,
518 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
527 	g = &pmx->soc->groups[group];
529 	ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
534 	val = pmx_readl(pmx, bank, reg);
547 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
556 	g = &pmx->soc->groups[group];
562 		ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
567 		val = pmx_readl(pmx, bank, reg);
593 		pmx_writel(pmx, val, bank, reg);
617 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
624 	g = &pmx->soc->groups[group];
627 		ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
632 		val = pmx_readl(pmx, bank, reg);
673 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
679 	for (i = 0; i < pmx->soc->ngroups; ++i) {
680 		g = &pmx->soc->groups[i];
692 			val = pmx_readl(pmx, bank, reg);
694 			pmx_writel(pmx, val, bank, reg);
712 	struct tegra_pmx *pmx = dev_get_drvdata(dev);
713 	u32 *backup_regs = pmx->backup_regs;
718 	for (i = 0; i < pmx->nbanks; i++) {
720 		regs = pmx->regs[i];
725 	return pinctrl_force_sleep(pmx->pctl);
730 	struct tegra_pmx *pmx = dev_get_drvdata(dev);
731 	u32 *backup_regs = pmx->backup_regs;
736 	for (i = 0; i < pmx->nbanks; i++) {
738 		regs = pmx->regs[i];
744 	readl_relaxed(pmx->regs[0]);
752 static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx)
757 	np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);
771 	struct tegra_pmx *pmx;
778 	pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
779 	if (!pmx)
782 	pmx->dev = &pdev->dev;
783 	pmx->soc = soc_data;
789 	pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4,
790 				       sizeof(*pmx->group_pins), GFP_KERNEL);
791 	if (!pmx->group_pins)
794 	pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions,
795 				      sizeof(*pmx->functions), GFP_KERNEL);
796 	if (!pmx->functions)
799 	group_pins = pmx->group_pins;
801 	for (fn = 0; fn < pmx->soc->nfunctions; fn++) {
802 		struct tegra_function *func = &pmx->functions[fn];
804 		func->name = pmx->soc->functions[fn];
807 		for (gn = 0; gn < pmx->soc->ngroups; gn++) {
808 			const struct tegra_pingroup *g = &pmx->soc->groups[gn];
819 			BUG_ON(group_pins - pmx->group_pins >=
820 				pmx->soc->ngroups * 4);
826 	pmx->gpio_range.name = "Tegra GPIOs";
827 	pmx->gpio_range.id = 0;
828 	pmx->gpio_range.base = 0;
829 	pmx->gpio_range.npins = pmx->soc->ngpios;
831 	pmx->desc.pctlops = &tegra_pinctrl_ops;
832 	pmx->desc.pmxops = &tegra_pinmux_ops;
833 	pmx->desc.confops = &tegra_pinconf_ops;
834 	pmx->desc.owner = THIS_MODULE;
835 	pmx->desc.name = dev_name(&pdev->dev);
836 	pmx->desc.pins = pmx->soc->pins;
837 	pmx->desc.npins = pmx->soc->npins;
845 	pmx->nbanks = i;
847 	pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
849 	if (!pmx->regs)
852 	pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
854 	if (!pmx->backup_regs)
857 	for (i = 0; i < pmx->nbanks; i++) {
858 		pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);
859 		if (IS_ERR(pmx->regs[i]))
860 			return PTR_ERR(pmx->regs[i]);
863 	pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx);
864 	if (IS_ERR(pmx->pctl)) {
866 		return PTR_ERR(pmx->pctl);
869 	tegra_pinctrl_clear_parked_bits(pmx);
871 	if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
872 		pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range);
874 	platform_set_drvdata(pdev, pmx);