Lines Matching refs:padctl
96 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
99 writel(value, padctl->regs + offset);
102 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
105 return readl(padctl->regs + offset);
110 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
112 return padctl->soc->num_pins;
118 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
120 return padctl->soc->pins[group].name;
153 static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
185 err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
203 err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
210 err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
218 err = pinctrl_utils_add_map_configs(padctl->pinctrl,
239 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
248 err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
270 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
272 return padctl->soc->num_functions;
279 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
281 return padctl->soc->functions[function].name;
289 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
291 *num_groups = padctl->soc->functions[function].num_groups;
292 *groups = padctl->soc->functions[function].groups;
301 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
306 lane = &padctl->soc->lanes[group];
315 value = padctl_readl(padctl, lane->offset);
318 padctl_writel(padctl, value, lane->offset);
334 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
340 lane = &padctl->soc->lanes[group];
348 value = padctl_readl(padctl, lane->offset);
359 dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
372 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
379 lane = &padctl->soc->lanes[group];
391 regval = padctl_readl(padctl, lane->offset);
398 padctl_writel(padctl, regval, lane->offset);
402 dev_err(padctl->dev,
480 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
484 mutex_lock(&padctl->lock);
486 if (padctl->enable++ > 0)
489 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
491 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
495 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
497 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
501 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
503 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
506 mutex_unlock(&padctl->lock);
510 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
514 mutex_lock(&padctl->lock);
516 if (WARN_ON(padctl->enable == 0))
519 if (--padctl->enable > 0)
522 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
524 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
528 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
530 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
534 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
536 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
539 mutex_unlock(&padctl->lock);
545 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
547 return tegra_xusb_padctl_enable(padctl);
552 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
554 return tegra_xusb_padctl_disable(padctl);
559 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
564 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
566 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
568 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
572 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
574 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
576 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
581 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
595 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
598 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
600 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
615 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
620 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
623 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
625 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
628 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
630 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
632 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
634 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
636 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
641 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
655 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
658 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
660 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
662 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
664 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
666 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
669 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
671 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
674 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
690 struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
696 if (index >= ARRAY_SIZE(padctl->phys))
699 return padctl->phys[index];
866 { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
877 struct tegra_xusb_padctl *padctl;
882 padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
883 if (!padctl)
886 platform_set_drvdata(pdev, padctl);
887 mutex_init(&padctl->lock);
888 padctl->dev = &pdev->dev;
897 padctl->soc = match->data;
899 padctl->regs = devm_platform_ioremap_resource(pdev, 0);
900 if (IS_ERR(padctl->regs))
901 return PTR_ERR(padctl->regs);
903 padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
904 if (IS_ERR(padctl->rst))
905 return PTR_ERR(padctl->rst);
907 err = reset_control_deassert(padctl->rst);
911 memset(&padctl->desc, 0, sizeof(padctl->desc));
912 padctl->desc.name = dev_name(padctl->dev);
913 padctl->desc.pins = tegra124_pins;
914 padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
915 padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
916 padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
917 padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
918 padctl->desc.owner = THIS_MODULE;
920 padctl->pinctrl = devm_pinctrl_register(&pdev->dev, &padctl->desc,
921 padctl);
922 if (IS_ERR(padctl->pinctrl)) {
924 err = PTR_ERR(padctl->pinctrl);
934 padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
935 phy_set_drvdata(phy, padctl);
943 padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
944 phy_set_drvdata(phy, padctl);
946 padctl->provider = devm_of_phy_provider_register(&pdev->dev,
948 if (IS_ERR(padctl->provider)) {
949 err = PTR_ERR(padctl->provider);
957 reset_control_assert(padctl->rst);
964 struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
967 err = reset_control_assert(padctl->rst);