Lines Matching defs:shift
62 u32 pin, u32 *reg, u32 *shift, u32 *mask)
69 *shift = offset % BITS_PER_TYPE(u32);
70 *mask = (BIT(MUX_FIELD_WIDTH) - 1) << *shift;
74 u32 pin, u32 *reg, u32 *shift, u32 *mask)
81 *shift = offset % BITS_PER_TYPE(u32);
82 *mask = (BIT(DATA_FIELD_WIDTH) - 1) << *shift;
86 u32 pin, u32 *reg, u32 *shift, u32 *mask)
93 *shift = offset % BITS_PER_TYPE(u32);
94 *mask = (BIT(pctl->dlevel_field_width) - 1) << *shift;
98 u32 pin, u32 *reg, u32 *shift, u32 *mask)
105 *shift = offset % BITS_PER_TYPE(u32);
106 *mask = (BIT(PULL_FIELD_WIDTH) - 1) << *shift;
516 u32 *reg, u32 *shift, u32 *mask)
520 sunxi_dlevel_reg(pctl, pin, reg, shift, mask);
526 sunxi_pull_reg(pctl, pin, reg, shift, mask);
541 u32 reg, shift, mask, val;
547 ret = sunxi_pconf_reg(pctl, pin, param, ®, &shift, &mask);
551 val = (readl(pctl->membase + reg) & mask) >> shift;
607 u32 arg, reg, shift, mask, val;
615 ret = sunxi_pconf_reg(pctl, pin, param, ®, &shift, &mask);
652 writel((readl(pctl->membase + reg) & ~mask) | val << shift,
779 u32 reg, shift, mask;
783 sunxi_mux_reg(pctl, pin, ®, &shift, &mask);
787 writel((readl(pctl->membase + reg) & ~mask) | config << shift,
927 u32 reg, shift, mask, val;
929 sunxi_data_reg(pctl, offset, ®, &shift, &mask);
934 val = (readl(pctl->membase + reg) & mask) >> shift;
946 u32 reg, shift, mask, val;
949 sunxi_data_reg(pctl, offset, ®, &shift, &mask);