Lines Matching refs:pctl
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
216 dev_err(pctl->dev, "pin %d not in range.\n", pin);
295 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
309 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
381 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
390 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
441 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
444 if (pctl->hwlock) {
445 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
448 dev_err(pctl->dev, "Can't get hwspinlock\n");
453 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
455 if (pctl->hwlock)
456 hwspin_unlock_in_atomic(pctl->hwlock);
468 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
477 spin_lock_irqsave(&pctl->irqmux_lock, flags);
479 if (pctl->irqmux_map & BIT(hwirq)) {
480 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
483 pctl->irqmux_map |= BIT(hwirq);
486 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
505 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
511 spin_lock_irqsave(&pctl->irqmux_lock, flags);
512 pctl->irqmux_map &= ~BIT(hwirq);
513 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
525 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
529 for (i = 0; i < pctl->ngroups; i++) {
530 struct stm32_pinctrl_group *grp = pctl->groups + i;
539 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
544 for (i = 0; i < pctl->npins; i++) {
545 const struct stm32_desc_pin *pin = pctl->pins + i;
560 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
565 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
576 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
591 struct stm32_pinctrl *pctl;
601 pctl = pinctrl_dev_get_drvdata(pctldev);
605 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
647 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
652 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
654 dev_err(pctl->dev, "unable to match pin %d to group\n",
660 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
707 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
709 return pctl->ngroups;
715 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
717 return pctl->groups[group].name;
725 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
727 *pins = (unsigned *)&pctl->groups[group].pin;
760 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
762 *groups = pctl->grp_names;
763 *num_groups = pctl->ngroups;
771 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
780 if (pctl->hwlock) {
781 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
784 dev_err(pctl->dev, "Can't get hwspinlock\n");
799 if (pctl->hwlock)
800 hwspin_unlock_in_atomic(pctl->hwlock);
836 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
837 struct stm32_pinctrl_group *g = pctl->groups + group;
843 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
849 dev_err(pctl->dev, "No gpio range defined.\n");
874 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
879 dev_err(pctl->dev, "No gpio range defined.\n");
884 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
906 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
913 if (pctl->hwlock) {
914 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
917 dev_err(pctl->dev, "Can't get hwspinlock\n");
927 if (pctl->hwlock)
928 hwspin_unlock_in_atomic(pctl->hwlock);
957 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
964 if (pctl->hwlock) {
965 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
968 dev_err(pctl->dev, "Can't get hwspinlock\n");
978 if (pctl->hwlock)
979 hwspin_unlock_in_atomic(pctl->hwlock);
1008 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1015 if (pctl->hwlock) {
1016 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1019 dev_err(pctl->dev, "Can't get hwspinlock\n");
1029 if (pctl->hwlock)
1030 hwspin_unlock_in_atomic(pctl->hwlock);
1080 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1087 dev_err(pctl->dev, "No gpio range defined.\n");
1095 dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
1133 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1135 *config = pctl->groups[group].config;
1143 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1144 struct stm32_pinctrl_group *g = &pctl->groups[group];
1179 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
1182 struct stm32_desc_pin *pins = pctl->pins;
1185 for (i = 0; i < pctl->npins; i++) {
1197 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1253 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
1277 static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl,
1286 if (stm32_pin_nb < pctl->npins) {
1287 pin_desc = pctl->pins + stm32_pin_nb;
1293 for (i = 0; i < pctl->npins; i++) {
1294 pin_desc = pctl->pins + i;
1301 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
1303 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1307 struct device *dev = pctl->dev;
1343 bank_nr = pctl->nbanks;
1351 pinctrl_add_gpio_range(pctl->pctl_dev,
1352 &pctl->banks[bank_nr].range);
1365 bank->secure_control = pctl->match_data->secure_control;
1368 if (pctl->domain) {
1372 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1389 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
1435 struct stm32_pinctrl *pctl)
1443 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1444 if (IS_ERR(pctl->regmap))
1445 return PTR_ERR(pctl->regmap);
1447 rm = pctl->regmap;
1469 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1470 if (IS_ERR(pctl->irqmux[i]))
1471 return PTR_ERR(pctl->irqmux[i]);
1479 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1482 pctl->ngroups = pctl->npins;
1485 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1486 sizeof(*pctl->groups), GFP_KERNEL);
1487 if (!pctl->groups)
1491 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1492 sizeof(*pctl->grp_names), GFP_KERNEL);
1493 if (!pctl->grp_names)
1496 for (i = 0; i < pctl->npins; i++) {
1497 const struct stm32_desc_pin *pin = pctl->pins + i;
1498 struct stm32_pinctrl_group *group = pctl->groups + i;
1502 pctl->grp_names[i] = pin->pin.name;
1508 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1514 for (i = 0; i < pctl->match_data->npins; i++) {
1515 p = pctl->match_data->pins + i;
1516 if (pctl->pkg && !(pctl->pkg & p->pkg))
1525 pctl->npins = nb_pins_available;
1535 struct stm32_pinctrl *pctl;
1544 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1545 if (!pctl)
1548 platform_set_drvdata(pdev, pctl);
1551 pctl->domain = stm32_pctrl_get_irq_domain(pdev);
1552 if (IS_ERR(pctl->domain))
1553 return PTR_ERR(pctl->domain);
1554 if (!pctl->domain)
1563 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1566 spin_lock_init(&pctl->irqmux_lock);
1568 pctl->dev = dev;
1569 pctl->match_data = match_data;
1572 if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
1573 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1575 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1576 sizeof(*pctl->pins), GFP_KERNEL);
1577 if (!pctl->pins)
1580 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1590 if (pctl->domain) {
1591 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1596 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1601 for (i = 0; i < pctl->npins; i++)
1602 pins[i] = pctl->pins[i].pin;
1604 pctl->pctl_desc.name = dev_name(&pdev->dev);
1605 pctl->pctl_desc.owner = THIS_MODULE;
1606 pctl->pctl_desc.pins = pins;
1607 pctl->pctl_desc.npins = pctl->npins;
1608 pctl->pctl_desc.link_consumers = true;
1609 pctl->pctl_desc.confops = &stm32_pconf_ops;
1610 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1611 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1612 pctl->dev = &pdev->dev;
1614 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1615 pctl);
1617 if (IS_ERR(pctl->pctl_dev)) {
1619 return PTR_ERR(pctl->pctl_dev);
1627 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1629 if (!pctl->banks)
1634 struct stm32_gpio_bank *bank = &pctl->banks[i];
1653 ret = stm32_gpiolib_register_bank(pctl, child);
1657 for (i = 0; i < pctl->nbanks; i++)
1658 clk_disable_unprepare(pctl->banks[i].clk);
1663 pctl->nbanks++;
1672 struct stm32_pinctrl *pctl, u32 pin)
1674 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1681 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1729 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1736 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1739 for (i = 0; i < pctl->nbanks; i++)
1740 clk_disable(pctl->banks[i].clk);
1747 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1748 struct stm32_pinctrl_group *g = pctl->groups;
1751 for (i = 0; i < pctl->nbanks; i++)
1752 clk_enable(pctl->banks[i].clk);
1754 for (i = 0; i < pctl->ngroups; i++, g++)
1755 stm32_pinctrl_restore_gpio_regs(pctl, g->pin);