Lines Matching refs:base
88 void __iomem *base;
204 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
220 return pinctrl_gpio_request(chip->base + offset);
225 pinctrl_gpio_free(chip->base + offset);
232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
244 return pinctrl_gpio_direction_input(chip->base + offset);
253 pinctrl_gpio_direction_output(chip->base + offset);
304 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
789 val = readl_relaxed(bank->base + alt_offset);
792 writel_relaxed(val, bank->base + alt_offset);
794 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
797 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
820 val = readl_relaxed(bank->base + alt_offset);
824 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
922 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
925 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
946 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
973 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
976 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
997 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
1024 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1027 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1048 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1065 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1068 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1320 bank->base = devm_ioremap_resource(dev, &res);
1321 if (IS_ERR(bank->base))
1322 return PTR_ERR(bank->base);
1336 bank->gpio_chip.base = args.args[1];
1344 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1348 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1358 bank->gpio_chip.base = -1;