Lines Matching refs:bank
157 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
164 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
173 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
180 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
183 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
184 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
187 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
190 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
191 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
196 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
199 stm32_gpio_backup_value(bank, offset, value);
204 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
237 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
239 __stm32_gpio_set(bank, offset, value);
250 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
252 __stm32_gpio_set(bank, offset, value);
261 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
264 fwspec.fwnode = bank->fwnode;
274 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
279 stm32_pmx_get_mode(bank, pin, &mode, &alt);
294 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
295 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
302 if (bank->secure_control) {
304 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
309 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
332 struct stm32_gpio_bank *bank = d->domain->host_data;
336 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
340 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
341 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
342 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
354 struct stm32_gpio_bank *bank = d->domain->host_data;
373 bank->irq_type[d->hwirq] = type;
380 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
381 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
384 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
388 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
400 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
402 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
440 struct stm32_gpio_bank *bank = d->host_data;
441 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
453 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
465 struct stm32_gpio_bank *bank = d->host_data;
468 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
496 bank);
504 struct stm32_gpio_bank *bank = d->host_data;
505 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
768 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
771 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
778 spin_lock_irqsave(&bank->lock, flags);
789 val = readl_relaxed(bank->base + alt_offset);
792 writel_relaxed(val, bank->base + alt_offset);
794 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
797 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
802 stm32_gpio_backup_mode(bank, pin, mode, alt);
805 spin_unlock_irqrestore(&bank->lock, flags);
810 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
818 spin_lock_irqsave(&bank->lock, flags);
820 val = readl_relaxed(bank->base + alt_offset);
824 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
828 spin_unlock_irqrestore(&bank->lock, flags);
839 struct stm32_gpio_bank *bank;
853 bank = gpiochip_get_data(range->gc);
859 return stm32_pmx_set_mode(bank, pin, mode, alt);
866 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
869 return stm32_pmx_set_mode(bank, pin, !input, 0);
903 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
906 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
911 spin_lock_irqsave(&bank->lock, flags);
922 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
925 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
930 stm32_gpio_backup_driving(bank, offset, drive);
933 spin_unlock_irqrestore(&bank->lock, flags);
938 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
944 spin_lock_irqsave(&bank->lock, flags);
946 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
949 spin_unlock_irqrestore(&bank->lock, flags);
954 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
957 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
962 spin_lock_irqsave(&bank->lock, flags);
973 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
976 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
981 stm32_gpio_backup_speed(bank, offset, speed);
984 spin_unlock_irqrestore(&bank->lock, flags);
989 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
995 spin_lock_irqsave(&bank->lock, flags);
997 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
1000 spin_unlock_irqrestore(&bank->lock, flags);
1005 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
1008 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1013 spin_lock_irqsave(&bank->lock, flags);
1024 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1027 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1032 stm32_gpio_backup_bias(bank, offset, bias);
1035 spin_unlock_irqrestore(&bank->lock, flags);
1040 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1046 spin_lock_irqsave(&bank->lock, flags);
1048 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1051 spin_unlock_irqrestore(&bank->lock, flags);
1056 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1062 spin_lock_irqsave(&bank->lock, flags);
1065 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1068 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1071 spin_unlock_irqrestore(&bank->lock, flags);
1082 struct stm32_gpio_bank *bank;
1091 bank = gpiochip_get_data(range->gc);
1101 ret = stm32_pconf_set_driving(bank, offset, 0);
1104 ret = stm32_pconf_set_driving(bank, offset, 1);
1107 ret = stm32_pconf_set_speed(bank, offset, arg);
1110 ret = stm32_pconf_set_bias(bank, offset, 0);
1113 ret = stm32_pconf_set_bias(bank, offset, 1);
1116 ret = stm32_pconf_set_bias(bank, offset, 2);
1119 __stm32_gpio_set(bank, offset, arg);
1200 struct stm32_gpio_bank *bank;
1215 bank = gpiochip_get_data(range->gc);
1223 stm32_pmx_get_mode(bank, offset, &mode, &alt);
1224 bias = stm32_pconf_get_bias(bank, offset);
1231 val = stm32_pconf_get(bank, offset, true);
1239 drive = stm32_pconf_get_driving(bank, offset);
1240 speed = stm32_pconf_get_speed(bank, offset);
1241 val = stm32_pconf_get(bank, offset, false);
1251 drive = stm32_pconf_get_driving(bank, offset);
1252 speed = stm32_pconf_get_speed(bank, offset);
1278 struct stm32_gpio_bank *bank,
1281 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;
1285 /* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */
1303 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1305 struct pinctrl_gpio_range *range = &bank->range;
1314 if (!IS_ERR(bank->rstc))
1315 reset_control_deassert(bank->rstc);
1320 bank->base = devm_ioremap_resource(dev, &res);
1321 if (IS_ERR(bank->base))
1322 return PTR_ERR(bank->base);
1324 err = clk_prepare_enable(bank->clk);
1330 bank->gpio_chip = stm32_gpio_template;
1332 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
1336 bank->gpio_chip.base = args.args[1];
1344 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1345 range->name = bank->gpio_chip.label;
1350 range->gc = &bank->gpio_chip;
1355 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
1358 bank->gpio_chip.base = -1;
1360 bank->gpio_chip.ngpio = npins;
1361 bank->gpio_chip.fwnode = fwnode;
1362 bank->gpio_chip.parent = dev;
1363 bank->bank_nr = bank_nr;
1364 bank->bank_ioport_nr = bank_ioport_nr;
1365 bank->secure_control = pctl->match_data->secure_control;
1366 spin_lock_init(&bank->lock);
1370 bank->fwnode = fwnode;
1372 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1373 bank->fwnode, &stm32_gpio_domain_ops,
1374 bank);
1376 if (!bank->domain) {
1389 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
1396 bank->gpio_chip.names = (const char * const *)names;
1398 err = gpiochip_add_data(&bank->gpio_chip, bank);
1404 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1408 clk_disable_unprepare(bank->clk);
1624 dev_err(dev, "at least one GPIO bank is required\n");
1634 struct stm32_gpio_bank *bank = &pctl->banks[i];
1637 bank->rstc = of_reset_control_get_exclusive(np, NULL);
1638 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1643 bank->clk = of_clk_get_by_name(np, NULL);
1644 if (IS_ERR(bank->clk)) {
1646 return dev_err_probe(dev, PTR_ERR(bank->clk),
1677 struct stm32_gpio_bank *bank;
1693 bank = gpiochip_get_data(range->gc);
1695 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1697 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1700 ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1705 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1707 __stm32_gpio_set(bank, offset, val);
1710 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1712 ret = stm32_pconf_set_driving(bank, offset, val);
1716 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1718 ret = stm32_pconf_set_speed(bank, offset, val);
1722 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1724 ret = stm32_pconf_set_bias(bank, offset, val);
1729 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);