Lines Matching refs:sfp
99 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
100 const struct jh7110_pinctrl_soc_info *info = sfp->info;
104 if (pin < sfp->gc.ngpio) {
107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset);
108 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
109 u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset);
127 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
128 struct device *dev = sfp->gc.parent;
152 mutex_lock(&sfp->mutex);
230 mutex_unlock(&sfp->mutex);
240 mutex_unlock(&sfp->mutex);
253 void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
256 const struct jh7110_pinctrl_soc_info *info = sfp->info;
268 reg_dout = sfp->base + info->dout_reg_base + offset;
269 reg_doen = sfp->base + info->doen_reg_base + offset;
276 reg_din = sfp->base + info->gpi_reg_base + ioffset;
283 raw_spin_lock_irqsave(&sfp->lock, flags);
292 raw_spin_unlock_irqrestore(&sfp->lock, flags);
299 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
300 const struct jh7110_pinctrl_soc_info *info = sfp->info;
314 info->jh7110_set_one_pin_mux(sfp,
351 static void jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp,
354 const struct jh7110_pinctrl_soc_info *info = sfp->info;
362 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
366 reg = sfp->base + padcfg_base + 4 * pin;
369 raw_spin_lock_irqsave(&sfp->lock, flags);
372 raw_spin_unlock_irqrestore(&sfp->lock, flags);
378 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
379 const struct jh7110_pinctrl_soc_info *info = sfp->info;
388 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
392 padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
448 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
512 jh7110_padcfg_rmw(sfp, group->pins[i], mask, value);
521 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
522 const struct jh7110_pinctrl_soc_info *info = sfp->info;
529 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
533 value = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
561 struct jh7110_pinctrl *sfp = container_of(gc,
563 const struct jh7110_pinctrl_soc_info *info = sfp->info;
566 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
577 struct jh7110_pinctrl *sfp = container_of(gc,
579 const struct jh7110_pinctrl_soc_info *info = sfp->info;
582 jh7110_padcfg_rmw(sfp, gpio,
587 info->jh7110_set_one_pin_mux(sfp, gpio,
596 struct jh7110_pinctrl *sfp = container_of(gc,
598 const struct jh7110_pinctrl_soc_info *info = sfp->info;
601 info->jh7110_set_one_pin_mux(sfp, gpio,
606 jh7110_padcfg_rmw(sfp, gpio,
614 struct jh7110_pinctrl *sfp = container_of(gc,
616 const struct jh7110_pinctrl_soc_info *info = sfp->info;
617 void __iomem *reg = sfp->base + info->gpioin_reg_base
626 struct jh7110_pinctrl *sfp = container_of(gc,
628 const struct jh7110_pinctrl_soc_info *info = sfp->info;
631 void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset;
636 raw_spin_lock_irqsave(&sfp->lock, flags);
639 raw_spin_unlock_irqrestore(&sfp->lock, flags);
645 struct jh7110_pinctrl *sfp = container_of(gc,
682 jh7110_padcfg_rmw(sfp, gpio, mask, value);
688 struct jh7110_pinctrl *sfp = container_of(gc,
691 sfp->gpios.name = sfp->gc.label;
692 sfp->gpios.base = sfp->gc.base;
693 sfp->gpios.pin_base = 0;
694 sfp->gpios.npins = sfp->gc.ngpio;
695 sfp->gpios.gc = &sfp->gc;
696 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
702 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
703 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
705 void __iomem *ic = sfp->base + irq_reg->ic_reg_base
711 raw_spin_lock_irqsave(&sfp->lock, flags);
715 raw_spin_unlock_irqrestore(&sfp->lock, flags);
720 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
721 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
723 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
729 raw_spin_lock_irqsave(&sfp->lock, flags);
732 raw_spin_unlock_irqrestore(&sfp->lock, flags);
734 gpiochip_disable_irq(&sfp->gc, d->hwirq);
739 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
740 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
742 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
744 void __iomem *ic = sfp->base + irq_reg->ic_reg_base
750 raw_spin_lock_irqsave(&sfp->lock, flags);
757 raw_spin_unlock_irqrestore(&sfp->lock, flags);
762 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
763 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
765 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
771 gpiochip_enable_irq(&sfp->gc, d->hwirq);
773 raw_spin_lock_irqsave(&sfp->lock, flags);
776 raw_spin_unlock_irqrestore(&sfp->lock, flags);
781 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
782 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
784 void __iomem *base = sfp->base + 4 * (gpio / 32);
824 raw_spin_lock_irqsave(&sfp->lock, flags);
833 raw_spin_unlock_irqrestore(&sfp->lock, flags);
856 struct jh7110_pinctrl *sfp;
871 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
872 if (!sfp)
876 sfp->saved_regs = devm_kcalloc(dev, info->nsaved_regs,
877 sizeof(*sfp->saved_regs), GFP_KERNEL);
878 if (!sfp->saved_regs)
882 sfp->base = devm_platform_ioremap_resource(pdev, 0);
883 if (IS_ERR(sfp->base))
884 return PTR_ERR(sfp->base);
927 sfp->info = info;
928 sfp->dev = dev;
929 platform_set_drvdata(pdev, sfp);
930 sfp->gc.parent = dev;
931 raw_spin_lock_init(&sfp->lock);
932 mutex_init(&sfp->mutex);
936 sfp, &sfp->pctl);
941 sfp->gc.label = dev_name(dev);
942 sfp->gc.owner = THIS_MODULE;
943 sfp->gc.request = jh7110_gpio_request;
944 sfp->gc.free = jh7110_gpio_free;
945 sfp->gc.get_direction = jh7110_gpio_get_direction;
946 sfp->gc.direction_input = jh7110_gpio_direction_input;
947 sfp->gc.direction_output = jh7110_gpio_direction_output;
948 sfp->gc.get = jh7110_gpio_get;
949 sfp->gc.set = jh7110_gpio_set;
950 sfp->gc.set_config = jh7110_gpio_set_config;
951 sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges;
952 sfp->gc.base = info->gc_base;
953 sfp->gc.ngpio = info->ngpios;
955 jh7110_irq_chip.name = sfp->gc.label;
956 gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip);
957 sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler;
958 sfp->gc.irq.num_parents = 1;
959 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
960 sizeof(*sfp->gc.irq.parents),
962 if (!sfp->gc.irq.parents)
964 sfp->gc.irq.default_type = IRQ_TYPE_NONE;
965 sfp->gc.irq.handler = handle_bad_irq;
966 sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw;
971 sfp->gc.irq.parents[0] = ret;
973 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
977 dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio);
979 return pinctrl_enable(sfp->pctl);
985 struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);
989 raw_spin_lock_irqsave(&sfp->lock, flags);
990 for (i = 0 ; i < sfp->info->nsaved_regs ; i++)
991 sfp->saved_regs[i] = readl_relaxed(sfp->base + 4 * i);
993 raw_spin_unlock_irqrestore(&sfp->lock, flags);
999 struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);
1003 raw_spin_lock_irqsave(&sfp->lock, flags);
1004 for (i = 0 ; i < sfp->info->nsaved_regs ; i++)
1005 writel_relaxed(sfp->saved_regs[i], sfp->base + 4 * i);
1007 raw_spin_unlock_irqrestore(&sfp->lock, flags);