Lines Matching refs:sfp
151 * sfp->gpio.pin_base = PAD_INVALID_GPIO then
152 * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
216 static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,
219 return pin - sfp->gpios.pin_base;
222 static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,
225 return sfp->gpios.pin_base + gpio;
456 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
457 unsigned int gpio = starfive_pin_to_gpio(sfp, pin);
464 reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;
481 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
482 struct device *dev = sfp->gc.parent;
529 mutex_lock(&sfp->mutex);
562 pins[i] = starfive_gpio_to_pin(sfp, gpio);
623 mutex_unlock(&sfp->mutex);
630 mutex_unlock(&sfp->mutex);
646 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
647 struct device *dev = sfp->gc.parent;
671 reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
672 reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
674 reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;
678 raw_spin_lock_irqsave(&sfp->lock, flags);
683 raw_spin_unlock_irqrestore(&sfp->lock, flags);
697 static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,
700 void __iomem *reg = sfp->padctl + 4 * (pin / 2);
706 static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,
710 void __iomem *reg = sfp->padctl + 4 * (pin / 2);
716 dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);
718 raw_spin_lock_irqsave(&sfp->lock, flags);
721 raw_spin_unlock_irqrestore(&sfp->lock, flags);
744 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
746 u16 value = starfive_padctl_get(sfp, pin);
808 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
880 starfive_padctl_rmw(sfp, group->pins[i], mask, value);
889 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
890 u16 value = starfive_padctl_get(sfp, pin);
931 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
932 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
943 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
944 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
948 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
952 raw_spin_lock_irqsave(&sfp->lock, flags);
954 raw_spin_unlock_irqrestore(&sfp->lock, flags);
961 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
962 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
963 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
966 raw_spin_lock_irqsave(&sfp->lock, flags);
969 raw_spin_unlock_irqrestore(&sfp->lock, flags);
972 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
981 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
982 void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);
990 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
991 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
994 raw_spin_lock_irqsave(&sfp->lock, flags);
996 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1002 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1038 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
1044 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1046 sfp->gpios.name = sfp->gc.label;
1047 sfp->gpios.base = sfp->gc.base;
1049 * sfp->gpios.pin_base depends on the chosen signal group
1052 sfp->gpios.npins = NR_GPIOS;
1053 sfp->gpios.gc = &sfp->gc;
1054 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
1060 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1062 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1066 raw_spin_lock_irqsave(&sfp->lock, flags);
1068 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1073 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1075 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1080 raw_spin_lock_irqsave(&sfp->lock, flags);
1083 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1085 gpiochip_disable_irq(&sfp->gc, gpio);
1090 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1092 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1093 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1098 raw_spin_lock_irqsave(&sfp->lock, flags);
1102 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1107 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1109 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1114 gpiochip_enable_irq(&sfp->gc, gpio);
1116 raw_spin_lock_irqsave(&sfp->lock, flags);
1119 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1124 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1126 void __iomem *base = sfp->base + 4 * (gpio / 32);
1166 raw_spin_lock_irqsave(&sfp->lock, flags);
1173 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1190 struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
1197 mis = readl_relaxed(sfp->base + GPIOMIS + 0);
1199 generic_handle_domain_irq(sfp->gc.irq.domain, pin);
1201 mis = readl_relaxed(sfp->base + GPIOMIS + 4);
1203 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
1210 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1213 writel(0, sfp->base + GPIOIE + 0);
1214 writel(0, sfp->base + GPIOIE + 4);
1216 writel(~0U, sfp->base + GPIOIC + 0);
1217 writel(~0U, sfp->base + GPIOIC + 4);
1219 writel(1, sfp->base + GPIOEN);
1231 struct starfive_pinctrl *sfp;
1237 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
1238 if (!sfp)
1241 sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
1242 if (IS_ERR(sfp->base))
1243 return PTR_ERR(sfp->base);
1245 sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");
1246 if (IS_ERR(sfp->padctl))
1247 return PTR_ERR(sfp->padctl);
1274 platform_set_drvdata(pdev, sfp);
1275 sfp->gc.parent = dev;
1276 raw_spin_lock_init(&sfp->lock);
1277 mutex_init(&sfp->mutex);
1279 ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
1286 writel(value, sfp->padctl + IO_PADSHARE_SEL);
1289 value = readl(sfp->padctl + IO_PADSHARE_SEL);
1292 sfp->gpios.pin_base = PAD_INVALID_GPIO;
1295 sfp->gpios.pin_base = PAD_GPIO(0);
1298 sfp->gpios.pin_base = PAD_FUNC_SHARE(72);
1301 sfp->gpios.pin_base = PAD_FUNC_SHARE(70);
1304 sfp->gpios.pin_base = PAD_FUNC_SHARE(0);
1310 sfp->gc.label = dev_name(dev);
1311 sfp->gc.owner = THIS_MODULE;
1312 sfp->gc.request = starfive_gpio_request;
1313 sfp->gc.free = starfive_gpio_free;
1314 sfp->gc.get_direction = starfive_gpio_get_direction;
1315 sfp->gc.direction_input = starfive_gpio_direction_input;
1316 sfp->gc.direction_output = starfive_gpio_direction_output;
1317 sfp->gc.get = starfive_gpio_get;
1318 sfp->gc.set = starfive_gpio_set;
1319 sfp->gc.set_config = starfive_gpio_set_config;
1320 sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
1321 sfp->gc.base = -1;
1322 sfp->gc.ngpio = NR_GPIOS;
1324 gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);
1325 sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
1326 sfp->gc.irq.num_parents = 1;
1327 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
1328 sizeof(*sfp->gc.irq.parents), GFP_KERNEL);
1329 if (!sfp->gc.irq.parents)
1331 sfp->gc.irq.default_type = IRQ_TYPE_NONE;
1332 sfp->gc.irq.handler = handle_bad_irq;
1333 sfp->gc.irq.init_hw = starfive_gpio_init_hw;
1338 sfp->gc.irq.parents[0] = ret;
1340 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
1344 irq_domain_set_pm_device(sfp->gc.irq.domain, dev);
1347 return pinctrl_enable(sfp->pctl);