Lines Matching refs:pfc
8 #define DRV_NAME "sh-pfc"
39 struct sh_pfc *pfc;
49 return pmx->pfc->info->nr_groups;
57 return pmx->pfc->info->groups[selector].name;
65 *pins = pmx->pfc->info->groups[selector].pins;
66 *num_pins = pmx->pfc->info->groups[selector].nr_pins;
105 struct device *dev = pmx->pfc->dev;
243 struct device *dev = pmx->pfc->dev;
298 return pmx->pfc->info->nr_functions;
306 return pmx->pfc->info->functions[selector].name;
316 *groups = pmx->pfc->info->functions[selector].groups;
317 *num_groups = pmx->pfc->info->functions[selector].nr_groups;
326 struct sh_pfc *pfc = pmx->pfc;
327 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
334 spin_lock_irqsave(&pfc->lock, flags);
337 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
349 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
356 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
363 spin_unlock_irqrestore(&pfc->lock, flags);
372 struct sh_pfc *pfc = pmx->pfc;
373 int idx = sh_pfc_get_pin_index(pfc, offset);
378 spin_lock_irqsave(&pfc->lock, flags);
380 if (!pfc->gpio && !cfg->mux_mark) {
384 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
386 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
396 spin_unlock_irqrestore(&pfc->lock, flags);
406 struct sh_pfc *pfc = pmx->pfc;
407 int idx = sh_pfc_get_pin_index(pfc, offset);
411 spin_lock_irqsave(&pfc->lock, flags);
415 sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);
416 spin_unlock_irqrestore(&pfc->lock, flags);
425 struct sh_pfc *pfc = pmx->pfc;
427 int idx = sh_pfc_get_pin_index(pfc, offset);
428 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
442 spin_lock_irqsave(&pfc->lock, flags);
443 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
444 spin_unlock_irqrestore(&pfc->lock, flags);
461 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,
468 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
484 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
492 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
496 val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0);
504 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
514 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
528 spin_lock_irqsave(&pfc->lock, flags);
530 val = sh_pfc_read(pfc, reg);
534 sh_pfc_write(pfc, reg, val);
536 spin_unlock_irqrestore(&pfc->lock, flags);
542 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
545 int idx = sh_pfc_get_pin_index(pfc, _pin);
546 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
573 struct sh_pfc *pfc = pmx->pfc;
578 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
587 if (!pfc->info->ops || !pfc->info->ops->get_bias)
590 spin_lock_irqsave(&pfc->lock, flags);
591 bias = pfc->info->ops->get_bias(pfc, _pin);
592 spin_unlock_irqrestore(&pfc->lock, flags);
604 ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);
613 int idx = sh_pfc_get_pin_index(pfc, _pin);
614 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
619 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
622 bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);
626 val = sh_pfc_read(pfc, pocctrl);
648 struct sh_pfc *pfc = pmx->pfc;
656 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
663 if (!pfc->info->ops || !pfc->info->ops->set_bias)
666 spin_lock_irqsave(&pfc->lock, flags);
667 pfc->info->ops->set_bias(pfc, _pin, param);
668 spin_unlock_irqrestore(&pfc->lock, flags);
677 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
686 int idx = sh_pfc_get_pin_index(pfc, _pin);
687 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
692 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
695 bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);
706 spin_lock_irqsave(&pfc->lock, flags);
707 val = sh_pfc_read(pfc, pocctrl);
712 sh_pfc_write(pfc, pocctrl, val);
713 spin_unlock_irqrestore(&pfc->lock, flags);
735 pins = pmx->pfc->info->groups[group].pins;
736 num_pins = pmx->pfc->info->groups[group].nr_pins;
756 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
761 pmx->pins = devm_kcalloc(pfc->dev,
762 pfc->info->nr_pins, sizeof(*pmx->pins),
767 pmx->configs = devm_kcalloc(pfc->dev,
768 pfc->info->nr_pins, sizeof(*pmx->configs),
773 for (i = 0; i < pfc->info->nr_pins; ++i) {
774 const struct sh_pfc_pin *info = &pfc->info->pins[i];
785 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
790 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
794 pmx->pfc = pfc;
796 ret = sh_pfc_map_pins(pfc, pmx);
806 pmx->pctl_desc.npins = pfc->info->nr_pins;
808 ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,
811 dev_err(pfc->dev, "could not register: %i\n", ret);
839 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
844 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
849 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
851 else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))
856 if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
863 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
870 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
875 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
880 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
884 sh_pfc_write(pfc, reg->pud, updown);
887 sh_pfc_write(pfc, reg->puen, enable);
889 enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
893 sh_pfc_write(pfc, reg->pud, enable);
902 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
904 void __iomem *reg = pfc->windows->virt +
905 pfc->info->ops->pin_to_portcr(pin);
919 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
922 void __iomem *reg = pfc->windows->virt +
923 pfc->info->ops->pin_to_portcr(pin);