Lines Matching defs:pctrl
142 static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl,
148 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1);
149 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1);
152 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4;
156 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0);
157 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0);
164 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
181 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
184 rzv2m_pinctrl_set_pfc_mode(pctrl, RZV2M_PIN_ID_TO_PORT(pins[i]),
219 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
243 dev_err(pctrl->dev, "Invalid pins list in DT\n");
253 dev_err(pctrl->dev,
263 dev_err(pctrl->dev, "DT node must contain a config\n");
296 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
297 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
299 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
317 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
327 mutex_lock(&pctrl->mutex);
347 mutex_unlock(&pctrl->mutex);
354 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
361 mutex_unlock(&pctrl->mutex);
390 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
418 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
427 static int rzv2m_validate_gpio_pin(struct rzv2m_pinctrl *pctrl,
434 if (bit >= pincount || port >= pctrl->data->n_port_pins)
437 data = pctrl->data->port_pin_configs[port];
444 static void rzv2m_rmw_pin_config(struct rzv2m_pinctrl *pctrl, u32 offset,
447 void __iomem *addr = pctrl->base + offset;
451 spin_lock_irqsave(&pctrl->lock, flags);
454 spin_unlock_irqrestore(&pctrl->lock, flags);
461 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
463 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
483 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit))
499 switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) {
522 val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK;
548 arg = readl(pctrl->base + SR(port)) & BIT(bit);
565 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
566 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
587 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit))
614 rzv2m_rmw_pin_config(pctrl, PUPD(port), bit, PUPD_MASK, val);
653 rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index);
663 rzv2m_writel_we(pctrl->base + SR(port), bit, !arg);
752 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
761 rzv2m_pinctrl_set_pfc_mode(pctrl, port, bit, 0);
766 static void rzv2m_gpio_set_direction(struct rzv2m_pinctrl *pctrl, u32 port,
769 rzv2m_writel_we(pctrl->base + OE(port), bit, output);
770 rzv2m_writel_we(pctrl->base + IE(port), bit, !output);
775 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
779 if (!(readl(pctrl->base + IE(port)) & BIT(bit)))
788 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
792 rzv2m_gpio_set_direction(pctrl, port, bit, false);
800 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
804 rzv2m_writel_we(pctrl->base + DO(port), bit, !!value);
810 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
815 rzv2m_gpio_set_direction(pctrl, port, bit, true);
822 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
828 return !!(readl(pctrl->base + DI(port)) & BIT(bit));
830 return !!(readl(pctrl->base + DO(port)) & BIT(bit));
933 static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl)
935 struct device_node *np = pctrl->dev->of_node;
936 struct gpio_chip *chip = &pctrl->gpio_chip;
937 const char *name = dev_name(pctrl->dev);
943 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
948 of_args.args[2] != pctrl->data->n_port_pins) {
949 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
953 chip->names = pctrl->data->port_pins;
962 chip->parent = pctrl->dev;
967 pctrl->gpio_range.id = 0;
968 pctrl->gpio_range.pin_base = 0;
969 pctrl->gpio_range.base = 0;
970 pctrl->gpio_range.npins = chip->ngpio;
971 pctrl->gpio_range.name = chip->label;
972 pctrl->gpio_range.gc = chip;
973 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
975 dev_err(pctrl->dev, "failed to add GPIO controller\n");
979 dev_dbg(pctrl->dev, "Registered gpio controller\n");
984 static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl)
991 pctrl->desc.name = DRV_NAME;
992 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
993 pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops;
994 pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops;
995 pctrl->desc.confops = &rzv2m_pinctrl_confops;
996 pctrl->desc.owner = THIS_MODULE;
998 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
1002 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
1007 pctrl->pins = pins;
1008 pctrl->desc.pins = pins;
1010 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
1012 pins[i].name = pctrl->data->port_pins[i];
1015 pin_data[i] = pctrl->data->port_pin_configs[j];
1019 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
1020 unsigned int index = pctrl->data->n_port_pins + i;
1023 pins[index].name = pctrl->data->dedicated_pins[i].name;
1024 pin_data[index] = pctrl->data->dedicated_pins[i].config;
1028 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
1029 &pctrl->pctl);
1031 dev_err(pctrl->dev, "pinctrl registration failed\n");
1035 ret = pinctrl_enable(pctrl->pctl);
1037 dev_err(pctrl->dev, "pinctrl enable failed\n");
1041 ret = rzv2m_gpio_register(pctrl);
1043 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
1052 struct rzv2m_pinctrl *pctrl;
1056 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1057 if (!pctrl)
1060 pctrl->dev = &pdev->dev;
1062 pctrl->data = of_device_get_match_data(&pdev->dev);
1063 if (!pctrl->data)
1066 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1067 if (IS_ERR(pctrl->base))
1068 return PTR_ERR(pctrl->base);
1070 clk = devm_clk_get_enabled(pctrl->dev, NULL);
1072 return dev_err_probe(pctrl->dev, PTR_ERR(clk),
1075 spin_lock_init(&pctrl->lock);
1076 mutex_init(&pctrl->mutex);
1078 platform_set_drvdata(pdev, pctrl);
1080 ret = rzv2m_pinctrl_register(pctrl);
1084 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);