Lines Matching refs:state
108 * @is_enabled: Set to false when MPP should be put in high Z state.
176 static int pmic_mpp_read(struct pmic_mpp_state *state,
182 ret = regmap_read(state->map, pad->base + addr, &val);
184 dev_err(state->dev, "read 0x%x failed\n", addr);
191 static int pmic_mpp_write(struct pmic_mpp_state *state,
197 ret = regmap_write(state->map, pad->base + addr, val);
199 dev_err(state->dev, "write 0x%x failed\n", addr);
254 static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state,
298 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
304 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
313 ret = pmic_mpp_write_mode_ctl(state, pad);
319 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
404 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
477 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val);
484 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL,
492 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val);
496 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level);
500 ret = pmic_mpp_write_mode_ctl(state, pad);
504 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_SINK_CTL, pad->drive_strength);
510 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
516 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
533 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
564 struct pmic_mpp_state *state = gpiochip_get_data(chip);
569 return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
575 struct pmic_mpp_state *state = gpiochip_get_data(chip);
580 return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
585 struct pmic_mpp_state *state = gpiochip_get_data(chip);
589 pad = state->ctrl->desc->pins[pin].drv_data;
592 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
604 struct pmic_mpp_state *state = gpiochip_get_data(chip);
609 pmic_mpp_config_set(state->ctrl, pin, &config, 1);
627 struct pmic_mpp_state *state = gpiochip_get_data(chip);
631 pmic_mpp_config_dbg_show(state->ctrl, s, i);
647 static int pmic_mpp_populate(struct pmic_mpp_state *state,
653 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE);
658 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
663 subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE);
679 dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n",
684 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL);
730 dev_err(state->dev, "unknown MPP direction\n");
742 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL);
751 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
760 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL);
767 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL);
773 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL);
779 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL);
793 struct pmic_mpp_state *state = container_of(domain->host_data,
798 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
860 struct pmic_mpp_state *state;
875 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
876 if (!state)
879 platform_set_drvdata(pdev, state);
881 state->dev = &pdev->dev;
882 state->map = dev_get_regmap(dev->parent, NULL);
918 ret = pmic_mpp_populate(state, pad);
923 state->chip = pmic_mpp_gpio_template;
924 state->chip.parent = dev;
925 state->chip.base = -1;
926 state->chip.ngpio = npins;
927 state->chip.label = dev_name(dev);
928 state->chip.of_gpio_n_cells = 2;
929 state->chip.can_sleep = false;
931 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
932 if (IS_ERR(state->ctrl))
933 return PTR_ERR(state->ctrl);
935 parent_node = of_irq_find_parent(state->dev->of_node);
944 girq = &state->chip.irq;
948 girq->fwnode = dev_fwnode(state->dev);
955 ret = gpiochip_add_data(&state->chip, state);
957 dev_err(state->dev, "can't add gpio chip\n");
961 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
970 gpiochip_remove(&state->chip);
976 struct pmic_mpp_state *state = platform_get_drvdata(pdev);
978 gpiochip_remove(&state->chip);