Lines Matching defs:pctrl
65 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
67 return pctrl->data->nfunctions;
73 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
75 return pctrl->data->functions[function].name;
83 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
85 *groups = pctrl->data->functions[function].groups;
86 *num_qgroups = pctrl->data->functions[function].ngroups;
94 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
95 const struct lpi_pingroup *g = &pctrl->data->groups[group];
107 mutex_lock(&pctrl->lock);
108 val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
117 !test_and_set_bit(group, pctrl->ever_gpio)) {
118 u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG);
122 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
126 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
132 lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
133 mutex_unlock(&pctrl->lock);
192 struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
200 g = &pctrl->data->groups[group];
239 mutex_lock(&pctrl->lock);
241 sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
244 iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
246 mutex_unlock(&pctrl->lock);
259 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
262 mutex_lock(&pctrl->lock);
263 val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
270 lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
271 mutex_unlock(&pctrl->lock);
389 static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl)
393 for (i = 0; i < pctrl->data->npins; i++) {
394 const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;
396 ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,
406 pinctrl_generic_remove_group(pctrl->ctrl, i - 1);
415 struct lpi_pinctrl *pctrl;
418 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
419 if (!pctrl)
422 platform_set_drvdata(pdev, pctrl);
431 pctrl->data = data;
432 pctrl->dev = &pdev->dev;
434 pctrl->clks[0].id = "core";
435 pctrl->clks[1].id = "audio";
437 pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
438 if (IS_ERR(pctrl->tlmm_base))
439 return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
442 pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
443 if (IS_ERR(pctrl->slew_base))
444 return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
447 ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
451 ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
455 pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
456 pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
457 pctrl->desc.confops = &lpi_gpio_pinconf_ops;
458 pctrl->desc.owner = THIS_MODULE;
459 pctrl->desc.name = dev_name(dev);
460 pctrl->desc.pins = data->pins;
461 pctrl->desc.npins = data->npins;
462 pctrl->chip = lpi_gpio_template;
463 pctrl->chip.parent = dev;
464 pctrl->chip.base = -1;
465 pctrl->chip.ngpio = data->npins;
466 pctrl->chip.label = dev_name(dev);
467 pctrl->chip.can_sleep = false;
469 mutex_init(&pctrl->lock);
471 pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
472 if (IS_ERR(pctrl->ctrl)) {
473 ret = PTR_ERR(pctrl->ctrl);
478 ret = lpi_build_pin_desc_groups(pctrl);
482 ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
484 dev_err(pctrl->dev, "can't add gpio chip\n");
491 mutex_destroy(&pctrl->lock);
492 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
500 struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
503 mutex_destroy(&pctrl->lock);
504 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
506 for (i = 0; i < pctrl->data->npins; i++)
507 pinctrl_generic_remove_group(pctrl->ctrl, i);