Lines Matching defs:data
107 const struct sx150x_device_data *data;
374 if (pin >= pctl->data->npins)
378 if (pctl->data->model != SX150X_789)
381 return !strcmp(pctl->data->pins[pin].name, "oscio");
394 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
413 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
423 return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
431 pctl->data->pri.x789.reg_clock,
452 regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
464 pctl->data->reg_dir,
482 pctl->data->reg_dir,
548 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
552 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
557 for_each_set_bit(n, &status, pctl->data->ngpios)
576 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
577 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
608 unsigned int data;
615 pctl->data->pri.x789.reg_clock,
616 &data);
621 arg = (data & 0x1f) ? 1 : 0;
623 if ((data & 0x1f) == 0x1f)
625 else if ((data & 0x1f) == 0x10)
642 pctl->data->reg_pulldn,
643 &data);
644 data &= BIT(pin);
657 pctl->data->reg_pullup,
658 &data);
659 data &= BIT(pin);
671 if (pctl->data->model != SX150X_789)
675 pctl->data->pri.x789.reg_drain,
676 &data);
677 data &= BIT(pin);
682 if (!data)
689 if (pctl->data->model != SX150X_789)
693 pctl->data->pri.x789.reg_drain,
694 &data);
695 data &= BIT(pin);
700 if (data)
761 pctl->data->reg_pulldn,
767 pctl->data->reg_pullup,
776 pctl->data->reg_pullup,
785 pctl->data->reg_pulldn,
793 if (pctl->data->model != SX150X_789 ||
798 pctl->data->pri.x789.reg_drain,
806 if (pctl->data->model != SX150X_789 ||
811 pctl->data->pri.x789.reg_drain,
854 { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
855 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
856 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
857 { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
858 { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
859 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
860 { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
861 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
862 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
871 pctl->data->pri.x789.reg_reset,
877 pctl->data->pri.x789.reg_reset,
886 switch (pctl->data->model) {
888 reg = pctl->data->pri.x789.reg_misc;
892 reg = pctl->data->pri.x456.reg_advanced;
903 reg = pctl->data->pri.x123.reg_advanced;
907 WARN(1, "Unknown chip model %d\n", pctl->data->model);
917 [SX150X_789] = pctl->data->pri.x789.reg_polarity,
918 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
919 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
923 if (pctl->data->model == SX150X_789 &&
935 return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
941 const struct sx150x_device_data *data = pctl->data;
943 if (reg == data->reg_sense) {
949 return 2 * data->ngpios;
950 } else if ((data->model == SX150X_789 &&
951 (reg == data->pri.x789.reg_misc ||
952 reg == data->pri.x789.reg_clock ||
953 reg == data->pri.x789.reg_reset))
955 (data->model == SX150X_123 &&
956 reg == data->pri.x123.reg_advanced)
958 (data->model == SX150X_456 &&
959 data->pri.x456.reg_advanced &&
960 reg == data->pri.x456.reg_advanced)) {
963 return data->ngpios;
971 const struct sx150x_device_data *data = pctl->data;
980 * SX1503 and SX1506 deviate from that data layout, instead storing
992 if (reg == data->reg_sense &&
993 data->ngpios == 16 &&
994 (data->model == SX150X_123 ||
995 data->model == SX150X_456)) {
1101 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
1139 pctl->data = of_device_get_match_data(dev);
1141 pctl->data = (struct sx150x_device_data *)id->driver_data;
1143 if (!pctl->data)
1165 pctl->pinctrl_desc.pins = pctl->data->pins;
1166 pctl->pinctrl_desc.npins = pctl->data->npins;
1178 pctl->gpio.ngpio = pctl->data->npins;
1197 if (pctl->data->model != SX150X_789)
1252 0, 0, pctl->data->npins);