Lines Matching defs:bank
64 * There are two registers cfg0 and cfg1 in this style for each bank.
65 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
275 * of each gpio pin in a GPIO bank.
277 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
278 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
371 struct st_gpio_bank *bank = gpio_range_to_bank(range);
373 return &bank->pc;
668 static inline void __st_gpio_set(struct st_gpio_bank *bank,
672 writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
674 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
677 static void st_gpio_direction(struct st_gpio_bank *bank,
701 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
703 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
709 struct st_gpio_bank *bank = gpiochip_get_data(chip);
711 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
716 struct st_gpio_bank *bank = gpiochip_get_data(chip);
717 __st_gpio_set(bank, offset, value);
730 struct st_gpio_bank *bank = gpiochip_get_data(chip);
732 __st_gpio_set(bank, offset, value);
740 struct st_gpio_bank *bank = gpiochip_get_data(chip);
741 struct st_pio_control pc = bank->pc;
763 value = readl(bank->base + REG_PIO_PC(i));
924 struct st_gpio_bank *bank = gpio_range_to_bank(range);
926 * When a PIO bank is used in its primary function mode (altfunc = 0)
930 st_pctl_set_function(&bank->pc, gpio, 0);
931 st_gpio_direction(bank, gpio, input ?
1057 int bank, struct st_pio_control *pc)
1062 /* 2 registers per bank */
1063 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
1093 int bank, struct st_pio_control *pc)
1098 /* 8 registers per bank */
1099 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
1117 int bank, struct st_pio_control *pc)
1121 return st_pctl_dt_setup_retime_packed(info, bank, pc);
1123 return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
1130 struct regmap *regmap, int bank,
1133 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
1141 static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
1146 * For a given shared register like OE/PU/OD, there are 8 bits per bank
1150 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
1152 struct st_pio_control *pc = &info->banks[bank].pc;
1156 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
1157 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
1158 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
1159 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
1164 st_pctl_dt_setup_retime(info, bank, pc);
1170 phandle bank, unsigned int offset)
1177 np = of_find_node_by_phandle(bank);
1196 * <bank offset mux direction rt_type rt_delay rt_clk>
1201 /* bank pad direction val altfunction */
1207 phandle bank;
1239 /* <bank offset mux direction rt_type rt_delay rt_clk> */
1247 /* bank & offset */
1248 bank = be32_to_cpup(list++);
1250 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset);
1314 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1316 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK);
1323 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1326 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK);
1348 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1370 comp = st_gpio_get(&bank->gpio_chip, pin);
1377 spin_lock_irqsave(&bank->lock, flags);
1378 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
1380 bank->irq_edge_conf |= pin_edge_conf;
1381 spin_unlock_irqrestore(&bank->lock, flags);
1383 val = readl(bank->base + REG_PIO_PCOMP);
1386 writel(val, bank->base + REG_PIO_PCOMP);
1399 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1403 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1415 static void __gpio_irq_handler(struct st_gpio_bank *bank)
1421 spin_lock_irqsave(&bank->lock, flags);
1422 bank_edge_mask = bank->irq_edge_conf;
1423 spin_unlock_irqrestore(&bank->lock, flags);
1426 port_in = readl(bank->base + REG_PIO_PIN);
1427 port_comp = readl(bank->base + REG_PIO_PCOMP);
1428 port_mask = readl(bank->base + REG_PIO_PMASK);
1441 val = st_gpio_get(&bank->gpio_chip, n);
1444 val ? bank->base + REG_PIO_SET_PCOMP :
1445 bank->base + REG_PIO_CLR_PCOMP);
1452 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n);
1459 /* interrupt dedicated per bank */
1462 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1465 __gpio_irq_handler(bank);
1511 struct st_gpio_bank *bank = &info->banks[bank_nr];
1512 struct pinctrl_gpio_range *range = &bank->range;
1521 bank->base = devm_ioremap_resource(dev, &res);
1522 if (IS_ERR(bank->base))
1523 return PTR_ERR(bank->base);
1525 bank->gpio_chip = st_gpio_template;
1526 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1527 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1528 bank->gpio_chip.fwnode = of_fwnode_handle(np);
1529 bank->gpio_chip.parent = dev;
1530 spin_lock_init(&bank->lock);
1532 of_property_read_string(np, "st,bank-name", &range->name);
1533 bank->gpio_chip.label = range->name;
1537 range->npins = bank->gpio_chip.ngpio;
1538 range->gc = &bank->gpio_chip;
1541 * GPIO bank can have one of the two possible types of
1548 * | |----> [gpio-bank (n) ]
1549 * | |----> [gpio-bank (n + 1)]
1550 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
1551 * | |----> [gpio-bank (... )]
1552 * |_________|----> [gpio-bank (n + 7)]
1554 * Second type has a dedicated interrupt per each gpio bank.
1556 * [irqN]----> [gpio-bank (n)]
1565 dev_err(dev, "invalid IRQ for %pOF bank\n", np);
1570 dev_err(dev, "no irqmux for %pOF bank\n", np);
1574 girq = &bank->gpio_chip.irq;
1588 err = gpiochip_add_data(&bank->gpio_chip, bank);
1591 dev_info(dev, "%s bank added.\n", range->name);
1609 int i = 0, j = 0, k = 0, bank;
1618 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n");
1656 bank = 0;
1662 ret = st_gpiolib_register_bank(info, bank, child);
1668 k = info->banks[bank].range.pin_base;
1669 bank_name = info->banks[bank].range.name;
1682 st_parse_syscfgs(info, bank, child);
1683 bank++;