Lines Matching refs:val
837 static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)
839 writel(val, pctl->base + reg);
852 static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,
855 writel(val, bank->base + reg);
859 u32 reg, unsigned int bit, u32 val)
865 gpio_writel(bank, (0x10000 | val) << bit, reg);
952 u32 val;
965 val = pctl_readl(pctl, pg->mux_reg);
966 val &= ~(pg->mux_mask << pg->mux_shift);
967 val |= i << pg->mux_shift;
968 pctl_writel(pctl, val, pg->mux_reg);
978 val = pctl_readl(pctl, pf->scenario_reg);
979 val &= ~(pf->scenario_mask << pf->scenario_shift);
980 val |= i << pf->scenario_shift;
981 pctl_writel(pctl, val, pf->scenario_reg);
1004 u32 val, arg;
1008 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1009 arg = !!(val & PADS_SCHMITT_EN_BIT(pin));
1012 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1014 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;
1017 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1019 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;
1022 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1024 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;
1027 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1029 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;
1032 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1033 arg = !!(val & PADS_SLEW_RATE_BIT(pin));
1036 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
1038 switch (val & PADS_DRIVE_STRENGTH_MASK) {
1069 u32 drv, val, arg;
1078 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1080 val |= PADS_SCHMITT_EN_BIT(pin);
1082 val &= ~PADS_SCHMITT_EN_BIT(pin);
1083 pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));
1086 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1087 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1088 val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);
1089 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1092 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1093 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1094 val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);
1095 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1098 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1099 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1100 val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);
1101 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1104 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1105 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1106 val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);
1107 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1110 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1112 val |= PADS_SLEW_RATE_BIT(pin);
1114 val &= ~PADS_SLEW_RATE_BIT(pin);
1115 pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));
1118 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));
1119 val &= ~(PADS_DRIVE_STRENGTH_MASK <<
1140 val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);
1141 pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));